* Some cleanup.

* Patch by Stefan Roese, 15 May 2002:

  - Support for esd CPCI-405 Version 2 added.
  - esd FPGA booting reworked, Xilinx Spartan 2 support added.
  - I2C settings changed for esd boards (new version supported).
  - 405gp_pci: changed vga board handling.

* Patch by Nye Liu, 14 May 2002
  - fix some problems on ZUMA boards like
    non-standard mii reg (Intel LXT972A)
  - only allow stack below 256M (for configurations over 256M - ugly)
  - 74xx_7xx: unlock cache just before booting linux

diff --git a/CHANGELOG b/CHANGELOG
index 3f0671dd467c45b61d3220f2e5174e96c7c6520b..9d1f1c9d5b4a0d7ff203953dba06282ad1c29a36 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -14,6 +14,19 @@
 Modifications for 1.1.6:
 ======================================================================
 
+* Patch by Stefan Roese, 15 May 2002:
+
+  - Support for esd CPCI-405 Version 2 added.
+  - esd FPGA booting reworked, Xilinx Spartan 2 support added.
+  - I2C settings changed for esd boards (new version supported).
+  - 405gp_pci: changed vga board handling.
+
+* Patch by Nye Liu, 14 May 2002
+  - fix some problems on ZUMA boards like
+    non-standard mii reg (Intel LXT972A)
+  - only allow stack below 256M (for configurations over 256M - ugly)
+  - 74xx_7xx: unlock cache just before booting linux
+
 * Fixed flash problems on OXC board.
 
 * That ugly bug raised it's head again: Fixed mkimage bug that caused

diff --git a/MAKEALL b/MAKEALL
index 61f1a146691abf0ec598607ba99e73a6605791b6..9b6bdfe91c8e9c94382d0f63c969e03c30d95ae2 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -34,9 +34,10 @@ LIST_8xx="   \
 
 LIST_4xx="     \
        ADCIOP          AR405           CANBT           CPCI405         \
-       CPCIISER4       CRAYL1          DASA_SIM        DU405           \
-       ERIC            MIP405          OCRTC           ORSG            \
-       PIP405          W7OLMC          W7OLMG          WALNUT405       \
+       CPCI4052        CPCIISER4       CRAYL1          DASA_SIM        \
+       DU405           ERIC            MIP405          OCRTC           \
+       ORSG            PIP405          W7OLMC          W7OLMG          \
+       WALNUT405       \
 "
 
 #########################################################################

diff --git a/Makefile b/Makefile
index 1ebd2957210950de3a8d194a38fccd3b4fc906b2..835d5a3e0158342ac76ac929011c57e551ddcff9 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -508,8 +508,9 @@ CANBT_config:       unconfig
        echo "VENDOR = esd"     >>config.mk ;   \
        echo "#include <config_$(@:_config=).h>" >config.h
 
-CPCI405_config:        unconfig
-       @echo "Configuring for $(@:_config=) Board..." ; \
+CPCI405_config         \
+CPCI4052_config:       unconfig
+       @echo "Configuring for $(call xtract,$@) Board..." ; \
        cd ./include ;                          \
        echo "ARCH  = ppc"      > config.mk ;   \
        echo "BOARD = cpci405"  >>config.mk ;   \

diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c
index 7c27b43f2c2164cbd5582624fc0bf5c243dffb5d..78ceaade3ea1c8ca719814d90444be782f54e7f2 100644 (file)
--- a/board/esd/ar405/ar405.c
+++ b/board/esd/ar405/ar405.c
@@ -49,17 +49,19 @@ const unsigned char fpgadata[] =
 int board_pre_init (void)
 {
   int index, len, i;
+  int status;
 
 #ifdef FPGA_DEBUG
   /* set up serial port with default baudrate */
-  serial_init(0, CONFIG_BAUDRATE);
+  serial_init(get_gclk_freq(), CONFIG_BAUDRATE);
   console_init_f();
 #endif
 
   /*
    * Boot onboard FPGA
    */
-  if (fpga_boot_compressed() != 0)
+  status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
+  if (status != 0)
     {
       /* booting FPGA failed */
 #ifndef FPGA_DEBUG
@@ -67,7 +69,20 @@ int board_pre_init (void)
       serial_init(0, CONFIG_BAUDRATE);
       console_init_f();
 #endif
-      printf("\nFPGA: Booting failed!\n ");
+      printf("\nFPGA: Booting failed ");
+      switch (status)
+        {
+        case ERROR_FPGA_PRG_INIT_LOW:
+          printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+          break;
+        case ERROR_FPGA_PRG_INIT_HIGH:
+          printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+          break;
+        case ERROR_FPGA_PRG_DONE:
+          printf("(Timeout: DONE not high after programming FPGA)\n ");
+          break;
+        }
+
       /* display infos on fpgaimage */
       index = 15;
       for (i=0; i<4; i++)

diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c
index 517869c21a4351094aa285d3bf801dfd7da5662f..a4f6f8d99f9a3d58b2e40ccb8cfe1d7952ba660d 100644 (file)
--- a/board/esd/canbt/canbt.c
+++ b/board/esd/canbt/canbt.c
@@ -60,20 +60,20 @@ int board_pre_init (void)
 
 #ifdef FPGA_DEBUG
   /* set up serial port with default baudrate */
-  serial_init(0, CONFIG_BAUDRATE);
+  serial_init(get_gclk_freq(), CONFIG_BAUDRATE);
   console_init_f();
 #endif
 
   /*
    * Boot onboard FPGA
    */
-  status = fpga_boot_compressed();
+  status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
   if (status != 0)
     {
       /* booting FPGA failed */
 #ifndef FPGA_DEBUG
       /* set up serial port with default baudrate */
-      serial_init(0, CONFIG_BAUDRATE);
+      serial_init(get_gclk_freq(), CONFIG_BAUDRATE);
       console_init_f();
 #endif
       printf("\nFPGA: Booting failed ");

diff --git a/board/esd/common/fpga.c b/board/esd/common/fpga.c
index 906ccf5e640a46fbe16ffc25427f793cd18fc389..e15eb731bea3a4f36cfde84536d3ec7fd64be58e 100644 (file)
--- a/board/esd/common/fpga.c
+++ b/board/esd/common/fpga.c
@@ -1,6 +1,7 @@
 /*
  * (C) Copyright 2001
  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -27,19 +28,32 @@
 
 /* ------------------------------------------------------------------------- */
 
+#ifdef FPGA_DEBUG
+#define DBG(x...) printf(x)
+#else
+#define DBG(x...)
+#endif /* DEBUG */
+
 #define MAX_ONES               226
-#define FPGA_PRG_SLEEP         32        /* fpga program sleep-time */
 
 #define IBM405GP_GPIO0_OR      0xef600700  /* GPIO Output */
 #define IBM405GP_GPIO0_TCR     0xef600704  /* GPIO Three-State Control */
 #define IBM405GP_GPIO0_ODR     0xef600718  /* GPIO Open Drain */
 #define IBM405GP_GPIO0_IR      0xef60071c  /* GPIO Input */
 
-#define FPGA_PRG               0x04000000  /* FPGA program pin (ppc output) */
-#define FPGA_CLK               0x02000000  /* FPGA clk pin (ppc output)     */
-#define FPGA_DATA              0x01000000  /* FPGA data pin (ppc output)    */
-#define FPGA_DONE              0x00800000  /* FPGA done pin (ppc input)     */
-#define FPGA_INIT              0x00400000  /* FPGA init pin (pcc input)     */
+#ifdef CFG_FPGA_PRG
+# define FPGA_PRG              CFG_FPGA_PRG /* FPGA program pin (ppc output)*/
+# define FPGA_CLK              CFG_FPGA_CLK /* FPGA clk pin (ppc output)    */
+# define FPGA_DATA             CFG_FPGA_DATA /* FPGA data pin (ppc output)  */
+# define FPGA_DONE             CFG_FPGA_DONE /* FPGA done pin (ppc input)   */
+# define FPGA_INIT             CFG_FPGA_INIT /* FPGA init pin (ppc input)   */
+#else
+# define FPGA_PRG              0x04000000  /* FPGA program pin (ppc output) */
+# define FPGA_CLK              0x02000000  /* FPGA clk pin (ppc output)     */
+# define FPGA_DATA             0x01000000  /* FPGA data pin (ppc output)    */
+# define FPGA_DONE             0x00800000  /* FPGA done pin (ppc input)     */
+# define FPGA_INIT             0x00400000  /* FPGA init pin (ppc input)     */
+#endif
 
 #define ERROR_FPGA_PRG_INIT_LOW  -1        /* Timeout after PRG* asserted   */
 #define ERROR_FPGA_PRG_INIT_HIGH -2        /* Timeout after PRG* deasserted */
@@ -60,25 +74,37 @@
         SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
 
 
-static int fpga_boot_compressed(void)
+static int fpga_boot(unsigned char *fpgadata, int size)
 {
   int i,index,len;
+  int count;
+#ifdef CFG_FPGA_SPARTAN2
+  int j;
+#else
   unsigned char b;
-  int size = sizeof(fpgadata);
   int bit;
-  int start;
+#endif
 
   /* display infos on fpgaimage */
   index = 15;
   for (i=0; i<4; i++)
     {
       len = fpgadata[index];
-#ifdef FPGA_DEBUG
-      printf("FPGA: %s\n", &(fpgadata[index+1]));
-#endif
+      DBG("FPGA: %s\n", &(fpgadata[index+1]));
       index += len+3;
     }
 
+#ifdef CFG_FPGA_SPARTAN2
+  /* search for preamble 0xFFFFFFFF */
+  while (1)
+    {
+      if ((fpgadata[index] == 0xff) && (fpgadata[index+1] == 0xff) && 
+          (fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff))
+        break; /* preamble found */
+      else
+        index++;
+    }
+#else
   /* search for preamble 0xFF2X */
   for (index = 0; index < size-1 ; index++)
     {
@@ -86,12 +112,11 @@ static int fpga_boot_compressed(void)
        break;
     }
   index += 2;
-
-#ifdef FPGA_DEBUG
-  printf("FPGA: COMPRESSED configdata starts at position 0x%x\n",index);
-  printf("FPGA: length of fpga-data %d\n", size-index);
 #endif
 
+  DBG("FPGA: configdata starts at position 0x%x\n",index);
+  DBG("FPGA: length of fpga-data %d\n", size-index);
+
   /*
    * Setup port pins for fpga programming
    */
@@ -99,60 +124,72 @@ static int fpga_boot_compressed(void)
   out32(IBM405GP_GPIO0_TCR, FPGA_PRG | FPGA_CLK | FPGA_DATA);  /* setup for output        */
   out32(IBM405GP_GPIO0_OR,  FPGA_PRG | FPGA_CLK | FPGA_DATA);  /* set output pins to high */
 
-#ifdef FPGA_DEBUG
-  printf("%s\n",((in32(IBM405GP_GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
-#endif
+  DBG("%s, ",((in32(IBM405GP_GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
+  DBG("%s\n",((in32(IBM405GP_GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
 
   /*
    * Init fpga by asserting and deasserting PROGRAM*
    */
   SET_FPGA(FPGA_CLK | FPGA_DATA);
 
-  /* Setup timeout timer */
-  start = get_timer(0);
-
   /* Wait for FPGA init line low */
+  count = 0;
   while (in32(IBM405GP_GPIO0_IR) & FPGA_INIT)
     {
+      udelay(1000); /* wait 1ms */
       /* Check for timeout - 100us max, so use 3ms */
-      if (get_timer(start) > 3)
+      if (count++ > 3)
         {
-#ifdef FPGA_DEBUG
-          printf("FPGA: Booting failed!\n");
-#endif
+          DBG("FPGA: Booting failed!\n");
           return ERROR_FPGA_PRG_INIT_LOW;
         }
     }
 
-#ifdef FPGA_DEBUG
-  printf("%s\n",((in32(IBM405GP_GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
-#endif
+  DBG("%s, ",((in32(IBM405GP_GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
+  DBG("%s\n",((in32(IBM405GP_GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
 
   /* deassert PROGRAM* */
   SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 
   /* Wait for FPGA end of init period .  */
+  count = 0;
   while (!(in32(IBM405GP_GPIO0_IR) & FPGA_INIT))
     {
+      udelay(1000); /* wait 1ms */
       /* Check for timeout */
-      if (get_timer(start) > 3)
+      if (count++ > 3)
         {
-#ifdef FPGA_DEBUG
-          printf("FPGA: Booting failed!\n");
-#endif
+          DBG("FPGA: Booting failed!\n");
           return ERROR_FPGA_PRG_INIT_HIGH;
         }
     }
 
-#ifdef FPGA_DEBUG
-  printf("%s\n",((in32(IBM405GP_GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
-#endif
+  DBG("%s, ",((in32(IBM405GP_GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
+  DBG("%s\n",((in32(IBM405GP_GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
 
-#ifdef FPGA_DEBUG
-  printf("write configuration data into fpga\n");
-#endif
+  DBG("write configuration data into fpga\n");
   /* write configuration-data into fpga... */
 
+#ifdef CFG_FPGA_SPARTAN2
+  /*
+   * Load uncompressed image into fpga
+   */
+  for (i=index; i<size; i++)
+    {
+      for (j=0; j<8; j++)
+        {
+          if ((fpgadata[i] & 0x80) == 0x80)
+           {
+              FPGA_WRITE_1;
+           }
+          else
+           {
+              FPGA_WRITE_0;
+           }
+          fpgadata[i] <<= 1;
+        }
+    }
+#else
   /* send 0xff 0x20 */
   FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1;
   FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1;
@@ -198,33 +235,28 @@ static int fpga_boot_compressed(void)
           FPGA_WRITE_1;
         }
     }
-
-#ifdef FPGA_DEBUG
-  printf("%s\n",((in32(IBM405GP_GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
 #endif
 
+  DBG("%s, ",((in32(IBM405GP_GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
+  DBG("%s\n",((in32(IBM405GP_GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
+
   /*
    * Check if fpga's DONE signal - correctly booted ?
    */
 
-  /* Setup timer */
-  start = get_timer(0);
-
   /* Wait for FPGA end of programming period .  */
+  count = 0;
   while (!(in32(IBM405GP_GPIO0_IR) & FPGA_DONE))
     {
+      udelay(1000); /* wait 1ms */
       /* Check for timeout */
-      if (get_timer(start) > 3)
+      if (count++ > 3)
         {
-#ifdef FPGA_DEBUG
-          printf("FPGA: Booting failed!\n");
-#endif
+          DBG("FPGA: Booting failed!\n");
           return ERROR_FPGA_PRG_DONE;
         }
     }
 
-#ifdef FPGA_DEBUG
-  printf("FPGA: Booting successful!\n");
-#endif
+  DBG("FPGA: Booting successful!\n");
   return 0;
 }

diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index 1b48c8ceed41cdef1569554b9e7668f71e0cc1dc..667485261d749c58eb464e38c1a3470c8fc16e5a 100644 (file)
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -22,10 +22,10 @@
  */
 
 #include <ppcboot.h>
-#include "cpci405.h"
 #include <asm/processor.h>
 #include <command.h>
 #include <cmd_boot.h>
+#include <malloc.h>
 
 /* ------------------------------------------------------------------------- */
 
@@ -36,7 +36,11 @@
 /* fpga configuration data - generated by bin2cc */
 const unsigned char fpgadata[] =
 {
-#include "fpgadata.c"
+#ifdef CONFIG_CPCI405_VER2
+# include "fpgadata_cpci4052.c"
+#else
+# include "fpgadata_cpci405.c"
+#endif
 };
 
 /*
@@ -45,69 +49,89 @@ const unsigned char fpgadata[] =
 #include "../common/fpga.c"
 
 
+/* Prototypes */
+int version2(void);
+int gunzip(void *, int, unsigned char *, int *);
+
+
 int board_pre_init (void)
 {
+#ifndef CONFIG_CPCI405_VER2
   int index, len, i;
   int status;
+#endif
 
 #ifdef FPGA_DEBUG
   /* set up serial port with default baudrate */
-  serial_init(0, CONFIG_BAUDRATE);
+  serial_init(get_gclk_freq(), CONFIG_BAUDRATE);
   console_init_f();
 #endif
 
+  /*
+   * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
+   */
+  out32(IBM405GP_GPIO0_ODR, 0x00000000);                       /* no open drain pins      */
+  out32(IBM405GP_GPIO0_TCR, CFG_FPGA_PRG);                     /* setup for output        */
+  out32(IBM405GP_GPIO0_OR,  CFG_FPGA_PRG);                     /* set output pins to high */
+  out32(IBM405GP_GPIO0_OR, 0);                                 /* pull prg low            */
+
   /*
    * Boot onboard FPGA
    */
-  status = fpga_boot_compressed();
-  if (status != 0)
+#ifndef CONFIG_CPCI405_VER2
+  if (!version2())
     {
-      /* booting FPGA failed */
+      status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
+      if (status != 0)
+        {
+         /* booting FPGA failed */
 #ifndef FPGA_DEBUG
-      /* set up serial port with default baudrate */
-      serial_init(0, CONFIG_BAUDRATE);
-      console_init_f();
+         /* set up serial port with default baudrate */
+         serial_init(get_gclk_freq(), CONFIG_BAUDRATE);
+         console_init_f();
 #endif
-      printf("\nFPGA: Booting failed ");
-      switch (status)
-        {
-        case ERROR_FPGA_PRG_INIT_LOW:
-          printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
-          break;
-        case ERROR_FPGA_PRG_INIT_HIGH:
-          printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
-          break;
-        case ERROR_FPGA_PRG_DONE:
-          printf("(Timeout: DONE not high after programming FPGA)\n ");
-          break;
-        }
-
-      /* display infos on fpgaimage */
-      index = 15;
-      for (i=0; i<4; i++)
-       {
-         len = fpgadata[index];
-         printf("FPGA: %s\n", &(fpgadata[index+1]));
-         index += len+3;
-       }
-      putc ('\n');
-      /* delayed reboot */
-      for (i=20; i>0; i--)
-       {
-         printf("Rebooting in %2d seconds \r",i);
-         for (index=0;index<1000;index++)
-           udelay(1000);
+         printf("\nFPGA: Booting failed ");
+         switch (status)
+           {
+           case ERROR_FPGA_PRG_INIT_LOW:
+             printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+             break;
+           case ERROR_FPGA_PRG_INIT_HIGH:
+             printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+             break;
+           case ERROR_FPGA_PRG_DONE:
+             printf("(Timeout: DONE not high after programming FPGA)\n ");
+             break;
+           }
+
+         /* display infos on fpgaimage */
+         index = 15;
+         for (i=0; i<4; i++)
+           {
+             len = fpgadata[index];
+             printf("FPGA: %s\n", &(fpgadata[index+1]));
+             index += len+3;
+           }
+         putc ('\n');
+         /* delayed reboot */
+         for (i=20; i>0; i--)
+           {
+             printf("Rebooting in %2d seconds \r",i);
+             for (index=0;index<1000;index++)
+               udelay(1000);
+           }
+         putc ('\n');
+         do_reset(NULL, NULL, 0, 0, NULL);
        }
-      putc ('\n');
-      do_reset(NULL, NULL, 0, 0, NULL);
     }
+#endif /* !CONFIG_CPCI405_VER2 */
 
   /*
    * IRQ 0-15  405GP internally generated; active high; level sensitive
    * IRQ 16    405GP internally generated; active low; level sensitive
    * IRQ 17-24 RESERVED
    * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
-   * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+   * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive
    * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
    * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
    * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
@@ -130,11 +154,15 @@ int board_pre_init (void)
 
 int ctermm2(void)
 {
+#ifdef CONFIG_CPCI405_VER2
+  return 0;                           /* no, board is cpci405 */
+#else
   if ((*(unsigned char *)0xf0000400 == 0x00) &&
       (*(unsigned char *)0xf0000401 == 0x01))
     return 0;                           /* no, board is cpci405 */
   else
     return -1;                          /* yes, board is cterm-m2 */
+#endif
 }
 
 
@@ -147,6 +175,31 @@ int cpci405_host(void)
 }
 
 
+int version2(void)
+{
+  unsigned long cntrl0Reg;
+  unsigned long value;
+
+  /*
+   * Setup GPIO pins (CS2/GPIO11 as GPIO)
+   */
+  cntrl0Reg = mfdcr(cntrl0);
+  mtdcr(cntrl0, cntrl0Reg | 0x02000000);
+
+  value = in32(IBM405GP_GPIO0_IR) & 0x02000000;
+
+  /*
+   * Setup GPIO pins (CS2/GPIO11 as CS again)
+   */
+  mtdcr(cntrl0, cntrl0Reg);
+
+  if (value)
+    return -1;                          /* yes, board is version 2.x */
+  else
+    return 0;                           /* no, board is version 1.x */
+}
+
+
 int misc_init_f(void)
 {
   return 0;  /* dummy implementation */
@@ -157,6 +210,97 @@ void misc_init_r(bd_t *bd)
 {
   char *       tmp;                    /* Temporary char pointer      */
 
+#ifdef CONFIG_CPCI405_VER2
+  unsigned char *dst;
+  ulong len;
+  int status;
+  int index;
+  int i;
+  unsigned long cntrl0Reg;
+
+  /*
+   * On CPCI-405 version 2 the environment is saved in eeprom!
+   * FPGA can be gzip compressed (malloc) and booted this late.
+   */
+
+  if (version2())
+    {
+      /*
+       * Setup GPIO pins (CS6+CS7 as GPIO)
+       */
+      cntrl0Reg = mfdcr(cntrl0);
+      mtdcr(cntrl0, cntrl0Reg | 0x00300000);
+      
+      dst = malloc(CFG_FPGA_MAX_SIZE);
+      if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0)
+        {
+         printf ("GUNZIP ERROR - must RESET board to recover\n");
+         do_reset (NULL, NULL, 0, 0, NULL);
+       }
+
+      status = fpga_boot(dst, len);
+      if (status != 0)
+        {
+         printf("\nFPGA: Booting failed ");
+         switch (status)
+           {
+           case ERROR_FPGA_PRG_INIT_LOW:
+             printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+             break;
+           case ERROR_FPGA_PRG_INIT_HIGH:
+             printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+             break;
+           case ERROR_FPGA_PRG_DONE:
+             printf("(Timeout: DONE not high after programming FPGA)\n ");
+             break;
+           }
+
+         /* display infos on fpgaimage */
+         index = 15;
+         for (i=0; i<4; i++)
+           {
+             len = dst[index];
+             printf("FPGA: %s\n", &(dst[index+1]));
+             index += len+3;
+           }
+         putc ('\n');
+         /* delayed reboot */
+         for (i=20; i>0; i--)
+           {
+             printf("Rebooting in %2d seconds \r",i);
+             for (index=0;index<1000;index++)
+               udelay(1000);
+           }
+         putc ('\n');
+         do_reset(NULL, NULL, 0, 0, NULL);
+       }
+
+      /* restore gpio/cs settings */
+      mtdcr(cntrl0, cntrl0Reg);
+
+      puts("FPGA:  ");
+
+      /* display infos on fpgaimage */
+      index = 15;
+      for (i=0; i<4; i++)
+        {
+         len = dst[index];
+         printf("%s ", &(dst[index+1]));
+         index += len+3;
+       }
+      putc ('\n');
+
+      free(dst);
+    }
+  else
+    {
+      printf("\n*** PPCBoot Version does not match Board Version!\n");
+      printf("*** CPCI-405 Version 2.x detected!\n");
+      printf("*** Please use correct PPCBoot version (CPCI4052)!\n\n");
+    }
+
+#else /* CONFIG_CPCI405_VER2 */
+
   /*
    * Generate last byte of ip-addr from code-plug @ 0xf0000400
    */
@@ -180,6 +324,15 @@ void misc_init_r(bd_t *bd)
         }
     }
 
+  if (version2())
+    {
+      printf("\n*** PPCBoot Version does not match Board Version!\n");
+      printf("*** CPCI-405 Board Version 1.x detected!\n");
+      printf("*** Please use correct PPCBoot version (CPCI405)!\n\n");
+    }
+
+#endif /* CONFIG_CPCI405_VER2 */
+
   /*
    * Write ethernet addr in NVRAM for VxWorks
    */
@@ -194,8 +347,10 @@ void misc_init_r(bd_t *bd)
 
 int checkboard (void)
 {
+#ifndef CONFIG_CPCI405_VER2
     int index;
     int len;
+#endif
     unsigned char str[64];
     int i = getenv_r ("serial#", str, sizeof(str));
 
@@ -205,14 +360,28 @@ int checkboard (void)
     else
       puts(str);
 
+    if (version2())
+      printf(" (Ver 2.x, ");
+    else
+      printf(" (Ver 1.x, ");
+
+#if 0
+    if ((*(unsigned short *)((unsigned long)CFG_FPGA_BASE_ADDR) + CFG_FPGA_STATUS)
+       & CFG_FPGA_STATUS_FLASH)
+      printf("FLASH Bank A, ");
+    else
+      printf("FLASH Bank B, ");
+#endif
+           
     if (ctermm2())
-      printf(" (CTERM-M2 - Id=0x%02x)", *(unsigned char *)0xf0000400);
+      printf("CTERM-M2 - Id=0x%02x)", *(unsigned char *)0xf0000400);
     else
       if (cpci405_host())
-        printf(" (PCI Host Version)");
+        printf("PCI Host Version)");
       else
-        printf(" (PCI Adapter Version)");
+        printf("PCI Adapter Version)");
 
+#ifndef CONFIG_CPCI405_VER2
     puts("\nFPGA:  ");
 
     /* display infos on fpgaimage */
@@ -223,6 +392,7 @@ int checkboard (void)
         printf("%s ", &(fpgadata[index+1]));
         index += len+3;
       }
+#endif
 
     putc ('\n');
 
@@ -257,3 +427,25 @@ int testdram (void)
 }
 
 /* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_CPCI405_VER2
+#ifdef CONFIG_IDE_RESET
+
+void ide_set_reset(int on)
+{
+       volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
+
+       /*
+        * Assert or deassert CompactFlash Reset Pin
+        */
+       if (on) {               /* assert RESET */
+               *fpga_mode &= ~(CFG_FPGA_MODE_CF_RESET);
+       } else {                /* release RESET */
+               *fpga_mode |= CFG_FPGA_MODE_CF_RESET;
+       }
+}
+
+#endif /* CONFIG_IDE_RESET */
+#endif /* CONFIG_CPCI405_VER2 */
+
+/* ------------------------------------------------------------------------- */

diff --git a/board/esd/cpci405/cpci405.h b/board/esd/cpci405/cpci405.h
deleted file mode 100644 (file)
index 5fc313a..0000000
--- a/board/esd/cpci405/cpci405.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/****************************************************************************
- * FLASH Memory Map as used by TQ Monitor:
- *
- *                          Start Address    Length
- * +-----------------------+ 0x4000_0000     Start of Flash -----------------
- * | MON8xx code           | 0x4000_0100     Reset Vector
- * +-----------------------+ 0x400?_????
- * | (unused)              |
- * +-----------------------+ 0x4001_FF00
- * | Ethernet Addresses    |                 0x78
- * +-----------------------+ 0x4001_FF78
- * | (Reserved for MON8xx) |                 0x44
- * +-----------------------+ 0x4001_FFBC
- * | Lock Address          |                 0x04
- * +-----------------------+ 0x4001_FFC0                     ^
- * | Hardware Information  |                 0x40            | MON8xx
- * +=======================+ 0x4002_0000 (sector border)    -----------------
- * | Autostart Header      |                                 | Applications
- * | ...                   |                                 v
- *
- *****************************************************************************/

diff --git a/board/esd/cpci405/fpgadata.c b/board/esd/cpci405/fpgadata_cpci405.c
similarity index 100%
rename from board/esd/cpci405/fpgadata.c
rename to board/esd/cpci405/fpgadata_cpci405.c

diff --git a/board/esd/cpci405/fpgadata_cpci4052.c b/board/esd/cpci405/fpgadata_cpci4052.c
new file mode 100644 (file)
index 0000000..4a97e6b
--- /dev/null
+++ b/board/esd/cpci405/fpgadata_cpci4052.c
@@ -0,0 +1,692 @@
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+  0x35,0x5f,0x32,0x5f,0x30,0x31,0x2e,0x62,0x69,0x74,0x00,0xed,0x9c,0x7f,0x74,0x14,
+  0xd7,0x95,0xe7,0x6f,0xbd,0xaa,0x96,0x4a,0xdd,0x2d,0x75,0xa9,0x25,0x91,0x8e,0x0d,
+  0xb8,0xd4,0x12,0xb8,0xad,0x69,0x89,0xa6,0x65,0x63,0x8d,0xac,0xb4,0x9e,0x7e,0x40,
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+  0xe8,0x7b,0xb0,0x68,0xe9,0xa2,0x6d,0x22,0x37,0x6e,0xa6,0xbe,0x5f,0x88,0x7f,0x4d,
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+  0x92,0xdf,0x28,0x2f,0xe5,0xeb,0xd6,0xe1,0x33,0xf3,0xd4,0x88,0x4f,0x26,0x74,0x42,
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+  0x3e,0x53,0xe0,0x5c,0x9a,0xab,0x16,0x22,0x97,0x24,0xce,0x3a,0xce,0x79,0xf3,0xbe,
+  0x0e,0xc1,0x2b,0x85,0xbb,0xe4,0x4c,0x6b,0x44,0xd9,0x8c,0x46,0x08,0x0d,0x7b,0x1e,
+  0xd1,0xa5,0x48,0x17,0xa1,0x1d,0x4a,0x41,0x91,0x11,0x2d,0xe5,0xf0,0x59,0x28,0x6d,
+  0x35,0x9f,0x99,0x94,0x0a,0xa0,0x8d,0x29,0x79,0xa9,0x41,0x28,0x81,0x16,0xa6,0xa4,
+  0x94,0x90,0x00,0x56,0x6e,0xa1,0xcf,0x23,0x9a,0x51,0x22,0x12,0x29,0x85,0x5e,0x34,
+  0x64,0xeb,0x14,0x35,0x3e,0x13,0xf1,0xce,0x0c,0xce,0x17,0x7e,0x9a,0x0d,0xe7,0xbf,
+  0x1a,0x2a,0xb6,0x59,0x27,0x7c,0x4a,0xba,0xb7,0x6b,0x6e,0xfe,0x6f,0x1a,0x4a,0x4f,
+  0xa0,0xb1,0x32,0xff,0xf1,0x06,0x3b,0x26,0xa8,0xf0,0x29,0xe4,0xfc,0x4e,0xc4,0xbb,
+  0x70,0x44,0xe2,0xc6,0xf5,0x21,0x3b,0x3e,0x3b,0x96,0x2e,0xd3,0xf1,0x7e,0x57,0x48,
+  0x39,0x02,0x8b,0x71,0x7d,0x20,0xa1,0x8a,0x21,0xbb,0xef,0xd7,0xc0,0x42,0x56,0xa4,
+  0xce,0x49,0xc2,0x03,0x50,0xdd,0xfb,0x89,0x4c,0xb0,0x53,0x62,0x66,0x54,0x50,0x28,
+  0xe1,0x5f,0xf6,0x9c,0x24,0x21,0xf8,0x96,0x54,0xc9,0x42,0x78,0x1f,0xf6,0xdd,0x0c,
+  0x8a,0xa5,0x7f,0x2b,0x7d,0x03,0x4a,0xb6,0x7d,0x9c,0xc1,0x38,0x34,0x78,0x4a,0x04,
+  0x1e,0x33,0xf6,0x33,0x3f,0x0f,0xab,0xbb,0x8a,0x32,0x05,0x9d,0xca,0x3f,0x43,0x35,
+  0x2b,0xca,0xb4,0x76,0x82,0xfd,0x4c,0x41,0xe7,0x3c,0x0e,0x71,0x29,0x5f,0x03,0x14,
+  0xe4,0xbc,0xc0,0x14,0xfb,0xbd,0x03,0x3d,0x54,0xae,0x4a,0xfe,0xd2,0x36,0xe8,0x38,
+  0x54,0x1e,0x5b,0xea,0x17,0xac,0xbe,0x53,0x8c,0x2e,0x5c,0x46,0x55,0x8f,0x8c,0x2f,
+  0xeb,0x76,0x6e,0xf0,0x36,0xf3,0xbd,0x1b,0x78,0x67,0xa8,0x7b,0x04,0xd0,0x39,0x8f,
+  0xc1,0x2a,0xd8,0xcf,0xd4,0xf1,0xae,0xca,0x32,0x0f,0x4f,0xe4,0x7c,0x44,0x06,0xdb,
+  0xcf,0x16,0x29,0x45,0xf9,0xf4,0x29,0xed,0x2a,0x48,0xb5,0xa0,0x21,0xd9,0xfd,0xe3,
+  0x6b,0x08,0xdf,0xa9,0x24,0xc8,0xeb,0x82,0x6a,0x78,0x98,0xff,0xa6,0x05,0xe7,0xbd,
+  0x77,0x16,0xd4,0x80,0x97,0x7d,0x25,0xa3,0x0c,0x90,0x08,0xbe,0x5f,0x92,0xb1,0xe3,
+  0xb3,0x03,0x3f,0xba,0xaa,0x43,0xa6,0xe4,0x46,0xfe,0x2b,0x5b,0x52,0xfe,0x49,0x52,
+  0x6e,0xfe,0xa6,0x28,0x1e,0xbb,0x12,0x2c,0x80,0x22,0x0d,0xd1,0xbf,0x1d,0xae,0x87,
+  0x62,0x4a,0xbe,0x0e,0x56,0xad,0x84,0xc7,0xe7,0x2a,0x2d,0xa4,0x2c,0x8b,0x0a,0x1b,
+  0xa5,0xd4,0xa1,0x50,0x1a,0x07,0xc1,0x89,0x4f,0x7e,0x16,0x42,0x56,0x88,0xa2,0xf0,
+  0x89,0x86,0xf3,0x28,0xe6,0x1a,0xcf,0x24,0xc7,0x3b,0xe3,0x78,0x6f,0x4f,0x71,0xce,
+  0x97,0x96,0x3a,0xe3,0x89,0x99,0x16,0xe2,0xdd,0x53,0xbf,0x8d,0xe6,0x3b,0x3e,0x5d,
+  0xde,0xbb,0x14,0xb6,0x39,0xe3,0x89,0x61,0x1e,0x2a,0x2f,0xc4,0x97,0x41,0xd5,0xdb,
+  0xa1,0x1c,0x39,0x6f,0x8f,0x27,0x72,0x49,0xe2,0x61,0xd9,0x81,0x9c,0x17,0x80,0xd1,
+  0x30,0xb8,0xe3,0x73,0xb9,0x58,0x26,0xb0,0x8e,0x9b,0x62,0xc9,0xe5,0x05,0x65,0xc0,
+  0x6e,0x5f,0x55,0x2e,0xdb,0xcf,0x14,0x92,0x0b,0xee,0x29,0x9d,0x0b,0x1f,0x57,0x1f,
+  0xce,0x45,0xe2,0x95,0x68,0x80,0x6b,0xcd,0x31,0xf0,0x8e,0x48,0xad,0x0a,0x25,0x87,
+  0x39,0x5b,0xff,0x2f,0x70,0xbe,0x96,0xff,0xf8,0xef,0xaf,0x7c,0x5f,0x3d,0xff,0xaf,
+  0xb7,0xaf,0xdc,0xc6,0xf1,0x5e,0xb6,0xcf,0xf0,0xe5,0x67,0x0f,0x2c,0xee,0xfd,0xc7,
+  0x0b,0x4e,0x1b,0xe9,0xc5,0x24,0x36,0xc2,0x93,0x58,0xcb,0x70,0xda,0xf8,0x34,0x07,
+  0x5d,0x53,0xd8,0x86,0x73,0xf5,0x82,0x7e,0x54,0x45,0x71,0x0c,0xe7,0xfa,0xb0,0xfb,
+  0xf8,0xaf,0x71,0xd0,0xb5,0x42,0x4f,0xcc,0x34,0xac,0x4f,0x33,0x88,0xaa,0xce,0x30,
+  0xcc,0x36,0x54,0x8b,0x2a,0xf4,0xf1,0x5f,0x1b,0x60,0x19,0x4e,0xdb,0xec,0x3b,0x9d,
+  0x36,0x6f,0x2f,0xd9,0x85,0x8b,0x77,0x8d,0x62,0x1b,0xae,0xfb,0x24,0xc2,0x5f,0xb8,
+  0xaa,0xd8,0x86,0xeb,0xf3,0x66,0xf5,0xcf,0x6e,0x53,0xf8,0xef,0x47,0x1b,0x81,0x7b,
+  0x61,0xae,0x66,0x1a,0x0a,0x91,0xec,0xfb,0x36,0xc6,0x2a,0x47,0xe4,0x7b,0xad,0xfb,
+  0xee,0x25,0x73,0xed,0xef,0xdc,0xf1,0x38,0xeb,0x02,0x5b,0x29,0xa1,0x71,0x85,0xf1,
+  0x34,0x3b,0xe2,0x1e,0x4f,0x85,0x89,0x31,0x18,0x81,0x7a,0xe7,0x67,0xfd,0x9a,0xfd,
+  0x3d,0xc5,0x0f,0xbe,0x9a,0x9a,0x66,0xff,0x5f,0x20,0xf0,0xbf,0xbd,0xed,0xcf,0xb8,
+  0x9a,0xa7,0xa6,0xa6,0xb4,0x69,0xc6,0xff,0x9b,0x6d,0x1f,0x1e,0xf3,0x33,0x63,0xc2,
+  0x75,0xe3,0x9f,0x15,0xf3,0xf5,0xb3,0xa2,0xfa,0xca,0x31,0xef,0xb4,0xc9,0xff,0xd1,
+  0x98,0x67,0x46,0xa8,0xcf,0x3d,0xb6,0x31,0x6e,0x18,0x43,0xce,0x7d,0x24,0xf8,0x01,
+  0xfd,0xc3,0x4f,0xee,0x56,0xec,0x18,0x9c,0x15,0xf3,0xd8,0xad,0x11,0xa7,0x7f,0x18,
+  0xfc,0x43,0x4e,0xcc,0x7f,0xe0,0x5c,0x81,0x0f,0xe9,0x1f,0x7c,0xe0,0x6c,0x07,0x1e,
+  0xf3,0x30,0xeb,0xba,0x1a,0xf3,0x7f,0x46,0xdb,0x07,0x5f,0xfc,0x77,0x39,0x12,0xfd,
+  0xef,0x96,0x9f,0xfd,0xa9,0xf7,0x5c,0xbd,0xae,0x5e,0x57,0xaf,0xab,0xd7,0xd5,0xeb,
+  0xea,0xf5,0xff,0xcb,0xa5,0xaf,0x93,0x44,0x5f,0x27,0xb5,0xff,0x6c,0x5f,0xae,0x5e,
+  0x57,0xaf,0xab,0xd7,0xd5,0xeb,0xea,0x75,0xf5,0xfa,0xcf,0xb8,0x62,0xfc,0x77,0xf7,
+  0x43,0xe0,0xa7,0x66,0x65,0x56,0x8c,0x01,0x2d,0xfc,0xf0,0x9f,0xd7,0x7f,0xce,0x13,
+  0x83,0x8c,0xe0,0xdc,0xbf,0x27,0x3d,0xd3,0xd7,0xff,0x05,0x2f,0x2f,0xc7,0xce,0xd5,
+  0x60,0x00,0x00,

diff --git a/board/esd/cpciiser4/cpciiser4.c b/board/esd/cpciiser4/cpciiser4.c
index 3274e8c92394f89251426817e0f587157a382ad7..09f157b2e2699863ee65c33ea9253fec0ab5f018 100644 (file)
--- a/board/esd/cpciiser4/cpciiser4.c
+++ b/board/esd/cpciiser4/cpciiser4.c
@@ -53,17 +53,19 @@ int board_pre_init (void)
 {
   int index, len, i;
   volatile unsigned char dummy;
+  int status;
 
 #ifdef FPGA_DEBUG
   /* set up serial port with default baudrate */
-  serial_init(0, CONFIG_BAUDRATE);
+  serial_init(get_gclk_freq(), CONFIG_BAUDRATE);
   console_init_f();
 #endif
 
   /*
    * Boot onboard FPGA
    */
-  if (fpga_boot_compressed() != 0)
+  status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
+  if (status != 0)
     {
       /* booting FPGA failed */
 #ifndef FPGA_DEBUG
@@ -71,7 +73,20 @@ int board_pre_init (void)
       serial_init(0, CONFIG_BAUDRATE);
       console_init_f();
 #endif
-      printf("\nFPGA: Booting failed!\n ");
+      printf("\nFPGA: Booting failed ");
+      switch (status)
+        {
+        case ERROR_FPGA_PRG_INIT_LOW:
+          printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+          break;
+        case ERROR_FPGA_PRG_INIT_HIGH:
+          printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+          break;
+        case ERROR_FPGA_PRG_DONE:
+          printf("(Timeout: DONE not high after programming FPGA)\n ");
+          break;
+        }
+
       /* display infos on fpgaimage */
       index = 15;
       for (i=0; i<4; i++)

diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c
index 015625d4364f55a02fdc01b901f755c1de19a4c4..279827bd171e9ac307f9d8a9d29553615f22937c 100644 (file)
--- a/board/esd/du405/du405.c
+++ b/board/esd/du405/du405.c
@@ -65,7 +65,7 @@ int board_pre_init (void)
   /*
    * Boot onboard FPGA
    */
-  status = fpga_boot_compressed();
+  status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
   if (status != 0)
     {
       /* booting FPGA failed */

diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c
index 923fd9f9a440805ff2f89c45262dbe7adb91e18e..7221b6354fd01a7c5a1020887ade38c7e685498d 100644 (file)
--- a/board/evb64260/eth.c
+++ b/board/evb64260/eth.c
@@ -79,7 +79,7 @@ struct eth_dev_s {
 };
 
 
-#ifdef ZUMA_NTL
+#ifdef CONFIG_INTEL_LXT97X
 /* for intel LXT972 */
 static const char ether_port_phy_addr[3]={0,1,2};
 #else
@@ -132,7 +132,7 @@ static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr)
                psr&2?"FD":"HD",
                psr&4?" FC":"nFC");
 
-#ifdef ZUMA_NTL /* non-standard mii reg (intel lxt972a) */
+#ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */
        {
         unsigned short mii_11;
        mii_11=miiphy_read_ret(ether_port_phy_addr[p->dev],0x11);
@@ -148,7 +148,7 @@ static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr)
                ""
                );
        }
-#endif /* ZUMA_NTL */
+#endif /* CONFIG_INTEL_LXT97X */
 #endif /* DEBUG */
     }
 }
@@ -484,7 +484,7 @@ gt6426x_eth_probe(void *v, bd_t *bis)
        for(i=0;i<255; i++)
            temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + reg_base +i);
 
-#ifdef ZUMA_NTL
+#ifdef CONFIG_INTEL_LXT97X
        /* for intel LXT972 */
 
        /* led 1: 0x1=txact
@@ -564,19 +564,19 @@ gt6426x_eth_probe(void *v, bd_t *bis)
        check_phy_state(p);
 #endif
 
-       printf("Waiting for link up..\n");
-       temp = 10000;
+       printf("%s: Waiting for link up..\n", wp->name);
+       temp = 10 * 1000;
        /* wait for link back up */
        while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + reg_base) & 8)
                        && (--temp > 0)){
-           udelay(10);
+           udelay(1000);       /* wait 1 ms */
        }
        if ( temp == 0) {
-               printf("Failed!\n");
+               printf("%s: Failed!\n", wp->name);
                return (0);
        }
 
-       printf("OK!\n");
+       printf("%s: OK!\n", wp->name);
 
        p->tdn = 0;
        p->rdn = 0;
@@ -655,7 +655,7 @@ gt6426x_eth_probe(void *v, bd_t *bis)
 
        /* Start Rx*/
        GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + reg_base, 0x00000080);
-       printf("gt6426x eth device %d init success \n", dev );
+       printf("%s: gt6426x eth device %d init success \n", wp->name, dev );
        return 1;
 }
 

diff --git a/board/evb64260/eth_addrtbl.c b/board/evb64260/eth_addrtbl.c
index c38d4d753d19cad9db143b0235f71808745405ac..404c5e9e3e6dea8770560e42950f9e4cbf1af386 100644 (file)
--- a/board/evb64260/eth_addrtbl.c
+++ b/board/evb64260/eth_addrtbl.c
@@ -13,10 +13,10 @@
 
 #ifdef CONFIG_GT_USE_MAC_HASH_TABLE
 
-static u32           addressTableHashMode[ GAL_ETH_DEVS ] = { 0, 0, 0 };
-static u32           addressTableHashSize[ GAL_ETH_DEVS ] = { 0, 0, 0 };
-static addrTblEntry *addressTableBase[     GAL_ETH_DEVS ] = { 0, 0, 0 };
-static void         *realAddrTableBase[    GAL_ETH_DEVS ] = { 0, 0, 0 };
+static u32           addressTableHashMode[ GAL_ETH_DEVS ] = { 0, };
+static u32           addressTableHashSize[ GAL_ETH_DEVS ] = { 0, };
+static addrTblEntry *addressTableBase[     GAL_ETH_DEVS ] = { 0, };
+static void         *realAddrTableBase[    GAL_ETH_DEVS ] = { 0, };
 
 static const u32 hashLength[ 2 ] = {
     (0x8000),             /* 8K * 4 entries */

diff --git a/board/evb64260/evb64260.c b/board/evb64260/evb64260.c
index 6e582d52e3dfd487221542c4a138368dd72d8f01..b083d28dc3d2879f9d203d4d0a6c35e8a03607bb 100644 (file)
--- a/board/evb64260/evb64260.c
+++ b/board/evb64260/evb64260.c
@@ -37,7 +37,7 @@
 #include "mpsc.h"
 #include "i2c.h"
 #include "64260.h"
-#ifdef ZUMA_NTL
+#ifdef CONFIG_ZUMA_V2
 extern void zuma_mbox_init(void);
 #endif
 
@@ -238,7 +238,7 @@ board_pre_init(void)
         * on-board sram on the eval board, and updates the correct
         * registers to boot from the sram. (device0)
         */
-#ifdef ZUMA_NTL
+#ifdef CONFIG_ZUMA_V2
        /* Zuma has no SRAM */
        sram_boot = 0;
 #else
@@ -310,7 +310,7 @@ misc_init_r(bd_t *bd)
        mpsc_init2();
 #endif
 
-#ifdef ZUMA_NTL
+#ifdef CONFIG_ZUMA_V2
        zuma_mbox_init();
 #endif
 
@@ -356,7 +356,7 @@ checkboard (void)
 void
 debug_led(int led, int mode)
 {
-#ifndef ZUMA_NTL
+#ifndef CONFIG_ZUMA_V2
         volatile int *addr = NULL;
         int dummy;
 
@@ -391,7 +391,7 @@ debug_led(int led, int mode)
         }
 
         dummy = *addr;
-#endif /* ZUMA_NTL */
+#endif /* CONFIG_ZUMA_V2 */
 }
 
 void

diff --git a/board/evb64260/flash.c b/board/evb64260/flash.c
index e07514619d1767866c8e5ce3633272f4224fe00c..6d979d3463545c2e5c416ca7aae16d3191cd4110 100644 (file)
--- a/board/evb64260/flash.c
+++ b/board/evb64260/flash.c
@@ -38,6 +38,9 @@
 #define FLASH_MAN_UNKNOWN 0xFFFF0000
 
 /* #define DEBUG */
+/* #define FLASH_ID_OVERRIDE */        /* Hack to set type to 040B if ROM emulator is installed.
+                                * Can be used to program a ROM in circuit if a programmer
+                                * is not available by swapping the rom out. */
 
 /* Intel flash commands */
 int flash_erase_intel(flash_info_t *info, int s_first, int s_last);
@@ -286,9 +289,16 @@ flash_get_size (int portwidth, vu_long *addr, flash_info_t *info)
            if(*caddr==0xf0) {
                /* this area is ROM */
                *caddr=save;
+#ifndef FLASH_ID_OVERRIDE
                info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN;
                info->sector_count = 8;
                info->size = 0x80000;
+#else
+               info->flash_id = FLASH_MAN_AMD + FLASH_AM040;
+               info->sector_count = 8;
+               info->size = 0x80000;
+               info->chipwidth=1;
+#endif
                flash_get_offsets(base, info);
                return info->size;
            }
@@ -322,9 +332,16 @@ flash_get_size (int portwidth, vu_long *addr, flash_info_t *info)
            (caddr[1] == old[1])) {
 
            /* this area is ROM */
+#ifndef FLASH_ID_OVERRIDE
            info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN;
            info->sector_count = 8;
            info->size = 0x80000;
+#else
+               info->flash_id = FLASH_MAN_AMD + FLASH_AM040;
+               info->sector_count = 8;
+               info->size = 0x80000;
+               info->chipwidth=1;
+#endif
            flash_get_offsets(base, info);
            return info->size;
 #ifdef DEBUG

diff --git a/board/evb64260/misc.S b/board/evb64260/misc.S
index 6e31731921d47b02ecb3b5e0e96094d59442cd8b..85cc252221ff1363b62d0ef0fd237d88c7ad90e0 100644 (file)
--- a/board/evb64260/misc.S
+++ b/board/evb64260/misc.S
@@ -145,8 +145,8 @@ board_asm_init:
        stwbrx  r6, r5, r3
 
        /* now, poll for the change */
-       lwbrx   r7, r5, r4
-1:     cmp     cr0, r7, r6
+1:     lwbrx   r7, r5, r4
+       cmp     cr0, r7, r6
        bne     1b
 
        /* done! */

diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c
index 10a90947f6f001210f86b6bc2fd22ef99eb1c878..ac5b3dcfc0634a984b561e80a522182c778b9193 100644 (file)
--- a/board/evb64260/mpsc.c
+++ b/board/evb64260/mpsc.c
@@ -270,7 +270,7 @@ mpsc_init(int baud)
 
        /* BRG CONFIG */
        galbrg_set_baudrate(CHANNEL, baud);
-#ifdef ZUMA_NTL
+#ifdef CONFIG_ZUMA_V2
        galbrg_set_clksrc(CHANNEL,0x8); /* connect TCLK -> BRG */
 #else
        galbrg_set_clksrc(CHANNEL,0);
@@ -383,7 +383,7 @@ galbrg_set_baudrate(int channel, int rate)
 
        galbrg_disable(channel);
 
-#ifdef ZUMA_NTL
+#ifdef CONFIG_ZUMA_V2
        /* from tclk */
        clock = (CFG_BUS_HZ/(16*rate)) - 1;
 #else

diff --git a/board/evb64260/pci.c b/board/evb64260/pci.c
index be284c4c227ef48ebb65432edfea5c85d50a2d5b..fb1494973cf97e128a749190557b23f7e6a0c5e2 100644 (file)
--- a/board/evb64260/pci.c
+++ b/board/evb64260/pci.c
@@ -7,11 +7,8 @@
 
 #include <galileo/pci.h>
 
-#undef DEBUG
-#undef IDE_SET_NATIVE_MODE
-
 static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
-#ifdef ZUMA_NTL
+#ifdef CONFIG_ZUMA_V2
     {0,0,0,0,0,0,0,29, [8 ... PCI_MAX_DEVICES-1]=0},
     {0,0,0,0,0,0,0,28, [8 ... PCI_MAX_DEVICES-1]=0}
 #else  /* EVB??? This is a guess */
@@ -534,7 +531,7 @@ static int gt_read_config_dword(struct pci_controller *hose,
                                pci_dev_t dev,
                                int offset, u32* value)
 {
-    *value = pciReadConfigReg((PCI_HOST) hose->cfg_addr, offset, dev);
+    *value = pciReadConfigReg((PCI_HOST) hose->cfg_addr, offset, PCI_DEV(dev));
     return 0;
 }
 
@@ -542,7 +539,7 @@ static int gt_write_config_dword(struct pci_controller *hose,
                                 pci_dev_t dev,
                                 int offset, u32 value)
 {
-    pciWriteConfigReg((PCI_HOST)hose->cfg_addr, offset, dev, value);
+    pciWriteConfigReg((PCI_HOST)hose->cfg_addr, offset, PCI_DEV(dev), value);
     return 0;
 }
 
@@ -640,6 +637,10 @@ pci_init(bd_t *bd)
     pciArbiterEnable(PCI_HOST0);
     pciParkingDisable(PCI_HOST0,1,1,1,1,1,1,1);
 
+    command = pciReadConfigReg(PCI_HOST0, PCI_COMMAND, SELF);
+    command |= PCI_COMMAND_MASTER;
+    pciWriteConfigReg(PCI_HOST0, PCI_COMMAND, SELF, command);
+
     pci0_hose.last_busno = pci_hose_scan(&pci0_hose);
 
     command = pciReadConfigReg(PCI_HOST0, PCI_COMMAND, SELF);
@@ -673,6 +674,10 @@ pci_init(bd_t *bd)
     pciArbiterEnable(PCI_HOST1);
     pciParkingDisable(PCI_HOST1,1,1,1,1,1,1,1);
 
+    command = pciReadConfigReg(PCI_HOST1, PCI_COMMAND, SELF);
+    command |= PCI_COMMAND_MASTER;
+    pciWriteConfigReg(PCI_HOST1, PCI_COMMAND, SELF, command);
+
     pci1_hose.last_busno = pci_hose_scan(&pci1_hose);
 
     command = pciReadConfigReg(PCI_HOST1, PCI_COMMAND, SELF);

diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c
index abc01864c344726c5eb154bb2fd77a410130e823..8a4ffdd3f6ee0476b129e08ec12448df909cf27a 100644 (file)
--- a/board/evb64260/sdram_init.c
+++ b/board/evb64260/sdram_init.c
@@ -35,7 +35,7 @@
 #include "i2c.h"
 #include "64260.h"
 
-#undef DEBUG
+/* #define     DEBUG */
 #define        MAP_PCI
 
 #ifdef DEBUG
@@ -44,30 +44,59 @@
 #define DP(x)
 #endif
 
-/* ------------------------------------------------------------------------- */
+#define GB         (1 << 30)
+
+/* structure to store the relevant information about an sdram bank */
+typedef struct sdram_info {
+       uchar drb_size;
+       uchar registered, ecc;
+       uchar tpar;
+       uchar tras_clocks;
+       uchar burst_len;
+       uchar banks, slot;
+       int size;       /* detected size, not from I2C but from dram_size() */
+} sdram_info_t;
 
-int
+#ifdef DEBUG
+void dump_dimm_info(struct sdram_info *d)
+{
+    static const char *ecc_legend[]={""," Parity"," ECC"};
+    printf("dimm%s %sDRAM: %dMibytes:\n",
+           ecc_legend[d->ecc],
+           d->registered?"R":"",
+           (d->size>>20));
+    printf("  drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
+           d->drb_size, d->tpar, d->tras_clocks, d->burst_len,
+           d->banks, d->slot);
+}
+#endif
+
+static int
 memory_map_bank(unsigned int bankNo,
                unsigned int bankBase,
                unsigned int bankLength)
 {
-#ifdef MAP_PCI
-       PCI_HOST host;
-#endif
-
-
 #ifdef DEBUG
        if (bankLength > 0) {
-               printf("\nmapping bank %d at %08x - %08x",
+               printf("mapping bank %d at %08x - %08x\n",
                       bankNo, bankBase, bankBase + bankLength - 1);
        } else {
-               printf("\nunmapping bank %d", bankNo);
+               printf("unmapping bank %d\n", bankNo);
        }
 #endif
 
        memoryMapBank(bankNo, bankBase, bankLength);
 
+       return 0;
+}
+
 #ifdef MAP_PCI
+static int
+memory_map_bank_pci(unsigned int bankNo,
+               unsigned int bankBase,
+               unsigned int bankLength)
+{
+       PCI_HOST host;
        for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
                const int features=
                        PREFETCH_ENABLE |
@@ -85,24 +114,15 @@ memory_map_bank(unsigned int bankNo,
 
                pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
        }
-#endif
        return 0;
 }
+#endif
 
-#define GB         (1 << 30)
+/* ------------------------------------------------------------------------- */
 
 /* much of this code is based on (or is) the code in the pip405 port */
 /* thanks go to the authors of said port - Josh */
 
-/* structure to store the relevant information about an sdram bank */
-typedef struct sdram_info {
-       uchar drb_size;
-       uchar registered, ecc;
-       uchar tpar;
-       uchar tras_clocks;
-       uchar burst_len;
-       uchar banks, slot;
-} sdram_info_t;
 
 /*
  * translate ns.ns/10 coding of SPD timing values
@@ -131,32 +151,37 @@ NSto10PS(unsigned char spd_byte)
        return(spd_byte*100);
 }
 
-/* This code reads the SPD chip on the sdram and populates
- * the array which is passed in with the relevant information */
+#ifdef CONFIG_ZUMA_V2
 static int
 check_dimm(uchar slot, sdram_info_t *info)
 {
-#ifdef ZUMA_NTL
-       /* zero all the values */
+        /* assume 2 dimms, 2 banks each 256M - we dont have an
+        * dimm i2c so rely on the detection routines later */
+
        memset(info, 0, sizeof(*info));
 
-       if (!slot) {
-           info->slot = 0;
-           info->banks = 1;
+       info->slot = slot;
+       info->banks = 2;        /* Detect later */
            info->registered = 0;
-           info->drb_size = 16; /* 16 - 256MBit, 32 - 512MBit */
+       info->drb_size = 32;    /* 16 - 256MBit, 32 - 512MBit
+                                  but doesn't matter, both do same
+                                  thing in setup_sdram() */
            info->tpar = 3;
            info->tras_clocks = 5;
            info->burst_len = 4;
-
 #ifdef CONFIG_ECC
-           /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
-           info->ecc = 2;
-#endif
-       }
+       info->ecc = 0;          /* Detect later */
+#endif /* CONFIG_ECC */
        return 0;
+}
 
-#else
+#else /* ! CONFIG_ZUMA_V2 */
+
+/* This code reads the SPD chip on the sdram and populates
+ * the array which is passed in with the relevant information */
+static int
+check_dimm(uchar slot, sdram_info_t *info)
+{
        uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
        int ret;
        uchar rows, cols, sdram_banks, supp_cal, width, cal_val;
@@ -250,23 +275,95 @@ check_dimm(uchar slot, sdram_info_t *info)
        /* compute the module DRB size */
        info->drb_size = (((1 << (rows + cols)) * sdram_banks) * width) / _16M;
 
+       DP(printf("drb_size set to: %d\n", info->drb_size));
+
        /* find the burst len */
        info->burst_len = data[16] & 0xf;
        if ((info->burst_len & 8) == 8) {
                info->burst_len = 1;
        } else if ((info->burst_len & 4) == 4) {
                info->burst_len = 0;
-       } else
+       } else {
                return 0;
+       }
 
        info->slot = slot;
+       return 0;
+}
+#endif /* ! CONFIG_ZUMA_V2 */
+
+static int
+setup_sdram_common(sdram_info_t info[2])
+{
+       ulong tmp;
+       int tpar=2, tras_clocks=5, registered=1, ecc=2;
+
+       if(!info[0].banks && !info[1].banks) return 0;
+
+       if(info[0].banks) {
+           if(info[0].tpar>tpar) tpar=info[0].tpar;
+           if(info[0].tras_clocks>tras_clocks) tras_clocks=info[0].tras_clocks;
+           if(!info[0].registered) registered=0;
+           if(info[0].ecc!=2) ecc=0;
+       }
+
+       if(info[1].banks) {
+           if(info[1].tpar>tpar) tpar=info[1].tpar;
+           if(info[1].tras_clocks>tras_clocks) tras_clocks=info[1].tras_clocks;
+           if(!info[1].registered) registered=0;
+           if(info[1].ecc!=2) ecc=0;
+       }
+
+       /* SDRAM configuration */
+       tmp = GTREGREAD(SDRAM_CONFIGURATION);
+
+       /* Turn on physical interleave if both DIMMs
+        * have even numbers of banks. */
+       if( (info[0].banks == 0 || info[0].banks == 2) &&
+           (info[1].banks == 0 || info[1].banks == 2) ) {
+           /* physical interleave on */
+           tmp &= ~(1 << 15);
+       } else {
+           /* physical interleave off */
+           tmp |= (1 << 15);
+       }
+       
+       tmp |= (registered << 17);
+
+       /* Use buffer 1 to return read data to the CPU
+        * See Res #12 */
+       tmp |= (1 << 26);
+
+       GT_REG_WRITE(SDRAM_CONFIGURATION, tmp);
+       DP(printf("SDRAM config: %08x\n",
+               GTREGREAD(SDRAM_CONFIGURATION)));
+
+       /* SDRAM timing */
+       tmp = (((tpar == 3) ? 2 : 1) |
+              (((tpar == 3) ? 2 : 1) << 2) |
+              (((tpar == 3) ? 2 : 1) << 4) |
+              (tras_clocks << 8));
+
+#ifdef CONFIG_ECC
+       /* Setup ECC */
+       if (ecc == 2) tmp |= 1<<13;
+#endif /* CONFIG_ECC */
+
+       GT_REG_WRITE(SDRAM_TIMING, tmp);
+       DP(printf("SDRAM timing: %08x (%d,%d,%d,%d)\n",
+               GTREGREAD(SDRAM_TIMING), tpar,tpar,tpar,tras_clocks));
+
+       /* SDRAM address decode register */
+       /* program this with the default value */
+       GT_REG_WRITE(SDRAM_ADDRESS_DECODE, 0x2);
+       DP(printf("SDRAM decode: %08x\n",
+               GTREGREAD(SDRAM_ADDRESS_DECODE)));
 
        return 0;
-#endif
 }
 
 /* sets up the GT properly with information passed in */
-int
+static int
 setup_sdram(sdram_info_t *info)
 {
        ulong tmp, check;
@@ -274,16 +371,13 @@ setup_sdram(sdram_info_t *info)
        int i;
 
        /* sanity checking */
-       if (! info->banks) {
-               printf("setup_sdram called with 0 banks\n");
-               return 1;
-       }
+       if (! info->banks) return 0;
 
        /* ---------------------------- */
        /* Program the GT with the discovered data */
 
        /* bank parameters */
-       tmp = 0;
+       tmp = (0xf<<16);        /* leave all virt bank pages open */
 
        DP(printf("drb_size: %d\n", info->drb_size));
        switch (info->drb_size) {
@@ -305,48 +399,13 @@ setup_sdram(sdram_info_t *info)
 
        /* SDRAM bank parameters */
        /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
-       DP(printf("setting up slot %d config with: %08lx\n", info->slot, tmp));
        GT_REG_WRITE(SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp);
        GT_REG_WRITE(SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp);
-
-       /* SDRAM configuration */
-       tmp = GTREGREAD(SDRAM_CONFIGURATION);
-
-       tmp |= (info->registered << 17);
-
-       /* Use buffer 1 to return read data to the CPU
-        * See Res #12 */
-       tmp |= (1 << 26);
-
-       GT_REG_WRITE(SDRAM_CONFIGURATION, tmp);
-
-       DP(printf("sdram_conf: %08x\n", GTREGREAD(SDRAM_CONFIGURATION)));
-
-       /* SDRAM timing */
-       DP(printf("setting timing parameters to: %d\n", info->tpar));
-
-       tmp = (((info->tpar == 3) ? 2 : 1) |
-              (((info->tpar == 3) ? 2 : 1) << 2) |
-              (((info->tpar == 3) ? 2 : 1) << 4) |
-              (info->tras_clocks << 8));
-
-       /* Is this right? RGF */
-       if (info->ecc == 2)
-               tmp |= 1<<13;
-
-       DP(printf("setting up sdram_timing with: %08lx\n", tmp));
-       GT_REG_WRITE(SDRAM_TIMING, tmp);
-
-       /* SDRAM address decode register */
-       /* program this with the default value */
-       GT_REG_WRITE(SDRAM_ADDRESS_DECODE, 0x2);
-
-       DP(printf("SDRAM address decode: %08x\n",
-                 GTREGREAD(SDRAM_ADDRESS_DECODE)));
+       DP(printf("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot, info->slot*2, (info->slot*2)+1, tmp));
 
        /* set the SDRAM configuration for each bank */
        for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) {
-               DP(printf("\n*** Running a MRS cycle for bank %d ***\n", i));
+               DP(printf("*** Running a MRS cycle for bank %d ***\n", i));
 
                /* map the bank */
                memory_map_bank(i, 0, GB/4);
@@ -368,6 +427,7 @@ setup_sdram(sdram_info_t *info)
 
                /* unmap the bank */
                memory_map_bank(i, 0, 0);
+               DP(printf("*** MRS cycle for bank %d done ***\n", i));
        }
 
        return 0;
@@ -423,11 +483,12 @@ dram_size(long int *base, long int maxsize)
 long int
 initdram(int board_type)
 {
-       int s0 = 0, s1 = 0;
-       int checkbank[4] = { [0 ... 3] = 0 };
-        ulong bank_no, realsize, total, check;
-       sdram_info_t dimm1, dimm2;
+       ulong checkbank[4] = { [0 ... 3] = 0 };
+       int bank_no;
+        ulong total;
        int nhr;
+       sdram_info_t dimm_info[2];
+
 
        /* first, use the SPD to get info about the SDRAM */
 
@@ -438,27 +499,27 @@ initdram(int board_type)
                printf("Skipping SDRAM setup due to NHR bit being set\n");
        } else {
                /* DIMM0 */
-               s0 = check_dimm(0, &dimm1);
+               check_dimm(0, &dimm_info[0]);
 
                /* DIMM1 */
-               s1 = check_dimm(1, &dimm2);
+               check_dimm(1, &dimm_info[1]);
 
+               /* unmap all banks */
                memory_map_bank(0, 0, 0);
                memory_map_bank(1, 0, 0);
                memory_map_bank(2, 0, 0);
                memory_map_bank(3, 0, 0);
 
                /* Now, program the GT with the correct values */
-               if (dimm1.tpar > dimm2.tpar)
-                       dimm2.tpar = dimm1.tpar;
-               else if(dimm2.tpar > dimm1.tpar)
-                       dimm1.tpar = dimm2.tpar;
+               if (setup_sdram_common(dimm_info)) {
+                       printf("Setup common failed.\n");
+               }
 
-               if (dimm1.banks && setup_sdram(&dimm1)) {
+               if (setup_sdram(&dimm_info[0])) {
                        printf("Setup for DIMM1 failed.\n");
                }
 
-               if (dimm2.banks && setup_sdram(&dimm2)) {
+               if (setup_sdram(&dimm_info[1])) {
                        printf("Setup for DIMM2 failed.\n");
                }
 
@@ -467,35 +528,83 @@ initdram(int board_type)
        }
        /* next, size the SDRAM banks */
 
-       realsize = total = 0;
-       check = GB/4;
-       if (dimm1.banks > 0) checkbank[0] = 1;
-       if (dimm1.banks > 1) checkbank[1] = 1;
-       if (dimm1.banks > 2)
+       total = 0;
+       if (dimm_info[0].banks > 0) checkbank[0] = 1;
+       if (dimm_info[0].banks > 1) checkbank[1] = 1;
+       if (dimm_info[0].banks > 2)
                printf("Error, SPD claims DIMM1 has >2 banks\n");
 
-       if (dimm2.banks > 0) checkbank[2] = 1;
-       if (dimm2.banks > 1) checkbank[3] = 1;
-       if (dimm2.banks > 2)
+       if (dimm_info[1].banks > 0) checkbank[2] = 1;
+       if (dimm_info[1].banks > 1) checkbank[3] = 1;
+       if (dimm_info[1].banks > 2)
                printf("Error, SPD claims DIMM2 has >2 banks\n");
 
+       /* Generic dram sizer: works even if we don't have i2c DIMMs,
+        * as long as the timing settings are more or less correct */
+
+       /*
+        * pass 1: size all the banks, using first bat (0-256M)
+        *         limitation: we only support 256M per bank due to 
+        *         us only having 1 BAT for all DRAM
+        */
        for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
                /* skip over banks that are not populated */
                if (! checkbank[bank_no])
                        continue;
 
-               if ((total + check) > CFG_GT_REGS)
-                       check = CFG_GT_REGS - total;
+               DP(printf("checking bank %d\n", bank_no));
 
-               memory_map_bank(bank_no, total, check);
-               realsize = dram_size((long int *)total, check);
-               memory_map_bank(bank_no, total, realsize);
+               memory_map_bank(bank_no, 0, GB/4);
+               checkbank[bank_no] = dram_size(NULL, GB/4);
+               memory_map_bank(bank_no, 0, 0);
 
-               total += realsize;
+               DP(printf("bank %d %08lx\n", bank_no, checkbank[bank_no]));
        }
 
+       /*
+        * pass 2: contiguously map each bank into physical address 
+        *         space.
+        */
+       dimm_info[0].banks=dimm_info[1].banks=0;
+       for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
+               if(!checkbank[bank_no]) continue;
+
+               dimm_info[bank_no/2].banks++;
+               dimm_info[bank_no/2].size+=checkbank[bank_no];
+
+               memory_map_bank(bank_no, total, checkbank[bank_no]);
+#ifdef MAP_PCI
+               memory_map_bank_pci(bank_no, total, checkbank[bank_no]);
+#endif
+               total += checkbank[bank_no]; 
+       }
+
+#ifdef CONFIG_ECC
+#ifdef CONFIG_ZUMA_V2
+       /*
+        * We always enable ECC when bank 2 and 3 are unpopulated
+        * If we 2 or 3 are populated, we CAN'T support ECC.
+        * (Zuma boards only support ECC in banks 0 and 1; assume that
+        * in that configuration, ECC chips are mounted, even for stacked
+        * chips)
+        */
+       if (checkbank[2]==0 && checkbank[3]==0) {
+               dimm_info[0].ecc=2;
+               GT_REG_WRITE(SDRAM_TIMING, GTREGREAD(SDRAM_TIMING) | (1 << 13));
+               /* TODO: do we have to run MRS cycles again? */
+       }
+#endif /* CONFIG_ZUMA_V2 */
+
        if (GTREGREAD(SDRAM_TIMING) & (1 << 13)) {
                puts("[ECC] ");
        }
-        return(total);
+#endif /* CONFIG_ECC */
+
+#ifdef DEBUG
+       dump_dimm_info(&dimm_info[0]);
+       dump_dimm_info(&dimm_info[1]);
+#endif
+       /* TODO: return at MOST 256M? */
+        /* return total > GB/4 ? GB/4 : total; */
+       return total;
 }

diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c
index 3d53a2fdc74157b905dd88f8134bef7ecc4b036c..b078abfc32bf3f2ab3bdfa0e0ff0c4e2347249e0 100644 (file)
--- a/board/evb64260/serial.c
+++ b/board/evb64260/serial.c
@@ -30,7 +30,11 @@
 #include <ppcboot.h>
 #include <command.h>
 #include <galileo/memory.h>
+
+#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
 #include <ns16550.h>
+#endif
+
 #include "serial.h"
 
 #include "mpsc.h"

diff --git a/board/oxc/oxc.c b/board/oxc/oxc.c
index 4475fc80e9638ee60c24436ea34a6683774c112b..43cbf589978054e65f67feaa2935b4c71f28e0af 100644 (file)
--- a/board/oxc/oxc.c
+++ b/board/oxc/oxc.c
@@ -113,9 +113,10 @@ void pci_init (bd_t * bd)
        pci_mpc824x_init(bd, &hose);
 }
 
-void board_pre_init(void)
+int board_pre_init(void)
 {
        *(volatile unsigned char *)(CFG_CPLD_RESET) = 0x89;
+       return 0;
 }
 
 #ifdef CONFIG_WATCHDOG

diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c
index 6019bd9065eff424b7e2875276af691d9265fcc7..41e07fed5cd7475dc3071583c20a8c087909f5f2 100644 (file)
--- a/board/pcippc2/pcippc2.c
+++ b/board/pcippc2/pcippc2.c
@@ -175,8 +175,6 @@ void watchdog_reset (void)
 #if (CONFIG_COMMANDS & CFG_CMD_BSP)
 int do_wd (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 {
-       uchar reg, val;
-
        switch (argc) {
        case 1:
                printf ("Watchdog timer status is %s\n",
@@ -207,4 +205,3 @@ int do_wd (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 
 #endif /* CFG_CMD_BSP */
 #endif /* CONFIG_WATCHDOG */
-

diff --git a/common/board.c b/common/board.c
index 5338c6b5b3d2e3d4d0f2ab390405956bcd384aa5..5413a450f3fcd3538ee7c71b3e54875687e87bac 100644 (file)
--- a/common/board.c
+++ b/common/board.c
@@ -355,7 +355,12 @@ board_init_f (ulong bootflag)
     if (CFG_MONITOR_LEN > len)
        len = CFG_MONITOR_LEN;
 
+#ifndef        CONFIG_VERY_BIG_RAM
     addr = CFG_SDRAM_BASE + dram_size;
+#else
+    /* only allow stack below 256M */
+    addr = CFG_SDRAM_BASE + (dram_size > 256<<20) ? 256<<20 : dram_size;
+#endif
 
 #ifdef CONFIG_PRAM
     /*

diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 295dee470a21ae9c680f412a43a7635ecbe37e04..546804a72a9ddebd8dea50d014d82716aad6d15e 100644 (file)
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -46,6 +46,10 @@
 # define SHOW_BOOT_PROGRESS(arg)
 #endif
 
+#ifdef CFG_INIT_RAM_LOCK
+#include <asm/cache.h>
+#endif
+
 int  gunzip (void *, int, unsigned char *, int *);
 
 static void *zalloc(void *, unsigned, unsigned);
@@ -509,6 +513,9 @@ do_bootm_linux (cmd_tbl_t *cmdtp, bd_t *bd, int flag,
 #endif
        SHOW_BOOT_PROGRESS (15);
 
+#ifdef CFG_INIT_RAM_LOCK
+       unlock_ram_in_cache();
+#endif
        /*
         * Linux Kernel Parameters:
         *   r3: ptr to board info data

diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S
index 7b98e44e07de28db2008d9d2117a15f23ce6277b..02b89b77fade86990b9bd41b5691ea7629255b16 100644 (file)
--- a/cpu/74xx_7xx/start.S
+++ b/cpu/74xx_7xx/start.S
@@ -329,23 +329,7 @@ in_flash:
        sync
 
 #ifdef CFG_INIT_RAM_LOCK
-       /* Allocate Initial RAM in data cache.
-        */
-       lis     r3, (CFG_INIT_RAM_ADDR & ~31)@h
-       ori     r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
-       li      r2, ((CFG_INIT_RAM_END & ~31) + \
-                    (CFG_INIT_RAM_ADDR & 31) + 31) / 32
-       mtctr   r2
-1:
-       dcbz    r0, r3
-       addi    r3, r3, 32
-       bdnz    1b
-
-       /* Lock the data cache */
-       mfspr   r0, HID0
-       ori     r0, r0, 0x1000
-       sync
-       mtspr   HID0, r0
+       bl      lock_ram_in_cache
        sync
 #endif
 
@@ -827,3 +811,49 @@ trap_reloc:
        isync
 
        blr
+
+#ifdef CFG_INIT_RAM_LOCK
+lock_ram_in_cache:
+       /* Allocate Initial RAM in data cache.
+        */
+       lis     r3, (CFG_INIT_RAM_ADDR & ~31)@h
+       ori     r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
+       li      r2, ((CFG_INIT_RAM_END & ~31) + \
+                    (CFG_INIT_RAM_ADDR & 31) + 31) / 32
+       mtctr   r2
+1:
+       dcbz    r0, r3
+       addi    r3, r3, 32
+       bdnz    1b
+
+       /* Lock the data cache */
+       mfspr   r0, HID0
+       ori     r0, r0, 0x1000
+       sync
+       mtspr   HID0, r0
+       sync
+       blr
+
+.globl unlock_ram_in_cache
+unlock_ram_in_cache:
+       /* invalidate the INIT_RAM section */
+       lis     r3, (CFG_INIT_RAM_ADDR & ~31)@h
+       ori     r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
+       li      r2, ((CFG_INIT_RAM_END & ~31) + \
+                    (CFG_INIT_RAM_ADDR & 31) + 31) / 32
+       mtctr   r2
+1:     icbi    r0, r3
+       addi    r3, r3, 32
+       bdnz    1b
+       sync                    /* Wait for all icbi to complete on bus */
+       isync
+
+       /* Unlock the data cache */
+       mfspr   r0, HID0
+       li      r3,0x1000
+       andc    r0,r0,r3
+       sync
+       mtspr   HID0, r0
+       sync
+       blr
+#endif

diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index 5d3d2fe864ca586ceda8421eb8c5b7d96603a56a..9331436ab10bc7ba20c8fcffd47e37b4baade2ff 100644 (file)
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -63,6 +63,8 @@
 |  26-Feb-02   stefan.roese@esd-electronics.com
 |              - Bug fixed in pci configuration (Andrew May)
 |              - Removed pci class code init for CPCI405 board
+|  15-May-02   stefan.roese@esd-electronics.com
+|              - New vga device handling
 +----------------------------------------------------------------------------*/
 
 #include <ppcboot.h>
@@ -309,7 +311,14 @@ void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, 
                         struct pci_config_table *entry)
 {
-  pciauto_setup_device(hose, dev, 6, hose->pci_fb, hose->pci_io);
+  unsigned int cmdstat = 0;
+
+  pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
+
+  /* always enable io space on vga boards */
+  pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
+  cmdstat |= PCI_COMMAND_IO;
+  pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
 }
 
 #if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405))

diff --git a/drivers/pci.c b/drivers/pci.c
index 9f89f566bcb9a12d63dcd439775a13dfd0d29fd1..176f4941d59c70fbb2caf3434d9144da1a80e31c 100644 (file)
--- a/drivers/pci.c
+++ b/drivers/pci.c
@@ -38,7 +38,6 @@
 #include <asm/io.h>
 #include <pci.h>
 
-#undef DEBUG
 #ifdef DEBUG
 #define DBG(x...) printf(x)
 #else
@@ -446,13 +445,14 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus)
 
                pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
 
-               if (!PCI_FUNC(dev))
-                       found_multi = header_type & 0x80;
-
                pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
 
                if (vendor != 0xffff && vendor != 0x0000)
                {
+
+                       if (!PCI_FUNC(dev))
+                               found_multi = header_type & 0x80;
+
                        DBG("PCI Scan: Found Bus %d, Device %d, Function %d\n",
                            PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
 

diff --git a/examples/eepro100_eeprom.c b/examples/eepro100_eeprom.c
index 13ee3cdc071aac784c072685802c07eb7b2b43c7..8604ce6136ab4f9ad595be931bb3ea6a3ff648c4 100644 (file)
--- a/examples/eepro100_eeprom.c
+++ b/examples/eepro100_eeprom.c
@@ -1,21 +1,24 @@
 /*
-       Copyright 1998-2001 by Donald Becker.
-       This software may be used and distributed according to the terms of
-       the GNU General Public License (GPL), incorporated herein by reference.
-       Contact the author for use under other terms.
-
-       This program must be compiled with "-O"!
-       See the bottom of this file for the suggested compile-command.
-
-       The author may be reached as becker@scyld.com, or C/O
-        Scyld Computing Corporation
-        410 Severn Ave., Suite 210
-        Annapolis MD 21403
-
-       Common-sense licensing statement: Using any portion of this program in
-       your own program means that you must give credit to the original author
-       and release the resulting code under the GPL.
-*/
+ * Copyright 1998-2001 by Donald Becker.
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL), incorporated herein by reference.
+ * Contact the author for use under other terms.
+ *
+ * This program must be compiled with "-O"!
+ * See the bottom of this file for the suggested compile-command.
+ *
+ * The author may be reached as becker@scyld.com, or C/O
+ *  Scyld Computing Corporation
+ *  410 Severn Ave., Suite 210
+ *  Annapolis MD 21403
+ *
+ * Common-sense licensing statement: Using any portion of this program in
+ * your own program means that you must give credit to the original author
+ * and release the resulting code under the GPL.
+ */
+
+#define _PPC_STRING_H_         /* avoid unnecessary str/mem functions */
+#define _LINUX_STRING_H_       /* avoid unnecessary str/mem functions */
 
 #include <ppcboot.h>
 #include <syscall.h>
@@ -25,15 +28,15 @@ static int reset_eeprom(unsigned long ioaddr, unsigned char *hwaddr);
 int eepro100_eeprom(void)
 {
        int ret = 0;
-       
+
        unsigned char hwaddr1[6] = { 0x00, 0x00, 0x02, 0x03, 0x04, 0x05 };
        unsigned char hwaddr2[6] = { 0x00, 0x00, 0x02, 0x03, 0x04, 0x06 };
-       
+
 #if defined(CONFIG_OXC)
        ret |= reset_eeprom(0x80000000, hwaddr1);
        ret |= reset_eeprom(0x81000000, hwaddr2);
 #endif
-       
+
        return ret;
 }
 
@@ -156,7 +159,7 @@ static void write_eeprom(long ioaddr, int index, int value, int addr_len)
        eeprom_busy_poll(ee_ioaddr);                    /* Typical 0 ticks */
        /* Enable programming modes. */
        do_eeprom_cmd(ioaddr, (0x4f << (addr_len-4)), 3 + addr_len);
-       /* Do the actual write. */ 
+       /* Do the actual write. */
        do_eeprom_cmd(ioaddr,
                                  (((EE_WRITE_CMD<<addr_len) | index)<<16) | (value & 0xffff),
                                  3 + addr_len + 16);
@@ -200,7 +203,7 @@ static int reset_eeprom(unsigned long ioaddr, unsigned char *hwaddr)
                        mon_printf("failed\n");
                        return 1;
                }
-               
+
        mon_printf("done\n");
        return 0;
 }

diff --git a/include/asm/cache.h b/include/asm/cache.h
index 35b074dad1a81af0af0097604143514a182117e1..5befab4d536894040b45939a259217e6e93ba688 100644 (file)
--- a/include/asm/cache.h
+++ b/include/asm/cache.h
@@ -35,6 +35,9 @@
 extern void flush_dcache_range(unsigned long start, unsigned long stop);
 extern void clean_dcache_range(unsigned long start, unsigned long stop);
 extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
+#ifdef CFG_INIT_RAM_LOCK
+extern void unlock_ram_in_cache(void);
+#endif /* CFG_INIT_RAM_LOCK */
 #endif /* __ASSEMBLY__ */
 
 /* prep registers for L2 */

diff --git a/include/cmd_bsp.h b/include/cmd_bsp.h
index 69b10dd5246a3c62656fcf5c0ae03ed8e3c1a505..df56de1d30a6f2b0fb5714f8e511ffc2f844a1ca 100644 (file)
--- a/include/cmd_bsp.h
+++ b/include/cmd_bsp.h
@@ -170,7 +170,7 @@ int do_crayL1 (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
 
 #if defined (CONFIG_EVB64260)
 /* ----- EVB64260 -------------------------------------------------------------*/
-#ifdef ZUMA_NTL
+#ifdef CONFIG_ZUMA_V2
 #define CMD_TBL_BSP  ZUMA_TBL_ENTRY
 
 #define ZUMA_TBL_ENTRY MK_CMD_TBL_ENTRY(                               \

diff --git a/include/config_CPCI405.h b/include/config_CPCI405.h
index bc3eb99cd0292790c92b19f17ab00546bbf4497b..ad5abd5cb8473f49837174a59d122445f4ecb319 100644 (file)
--- a/include/config_CPCI405.h
+++ b/include/config_CPCI405.h
@@ -244,6 +244,8 @@
 #define CFG_EEPROM_PAGE_WRITE_BITS 4   /* The Catalyst CAT24WC08 has   */
                                        /* 16 byte page write mode using*/
                                        /* last 4 bits of the address   */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE 
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
@@ -291,9 +293,16 @@
 #define CFG_EBC_PB5AP           0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
 #define CFG_EBC_PB5CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
 
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
 
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR       0xF0000500
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT           0x00400000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE           0x00800000  /* FPGA done pin (ppc input)     */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)

diff --git a/include/config_CPCI4052.h b/include/config_CPCI4052.h
new file mode 100644 (file)
index 0000000..94b645a
--- /dev/null
+++ b/include/config_CPCI4052.h
@@ -0,0 +1,364 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP           1       /* This is a PPC405 CPU         */
+#define CONFIG_4xx             1       /* ...member of PPC4xx family   */
+#define CONFIG_CPCI405         1       /* ...on a CPCI405 board        */
+#define CONFIG_CPCI405_VER2     1       /* ...version 2                 */
+
+#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
+
+#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
+
+#define CONFIG_BAUDRATE                9600
+#define CONFIG_BOOTDELAY       3       /* autoboot after 3 seconds     */
+
+#if 0
+#define CONFIG_PREBOOT                                                          \
+        "crc32 f0207004 ffc 0;"                                                 \
+        "if cmp 0 f0207000 1;"                                                  \
+        "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
+        "else;echo Old CRC is bad;fi"
+#endif
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_RAMBOOTCOMMAND                                                  \
+       "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) "     \
+       "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"    \
+       "bootm ffc00000 ffca0000"
+#define CONFIG_NFSBOOTCOMMAND                                                  \
+       "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "     \
+       "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"    \
+       "bootm ffc00000"
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#define CONFIG_LOADS_ECHO      1       /* echo on for serial download  */
+#define CFG_LOADS_BAUD_CHANGE  1       /* allow baudrate change        */
+
+#define CONFIG_MII             1       /* MII PHY management           */
+#define        CONFIG_PHY_ADDR         0       /* PHY address                  */
+
+#define CONFIG_RTC_M48T35A     1               /* ST Electronics M48 timekeeper */
+
+#define CONFIG_COMMANDS              ( CONFIG_CMD_DFL  | \
+                               CFG_CMD_PCI     | \
+                               CFG_CMD_IRQ     | \
+                               CFG_CMD_IDE     | \
+                               CFG_CMD_ELF     | \
+                               CFG_CMD_DATE    | \
+                               CFG_CMD_I2C     | \
+                               CFG_CMD_EEPROM  )
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef  CONFIG_WATCHDOG                        /* watchdog disabled            */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP                   /* undef to save memory         */
+#define CFG_PROMPT     "=> "           /* Monitor Command Prompt       */
+
+#undef CFG_HUSH_PARSER                 /* use "hush" command parser    */
+#ifdef CFG_HUSH_PARSER
+#define        CFG_PROMPT_HUSH_PS2     "> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define        CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
+#else
+#define        CFG_CBSIZE      256             /* Console I/O Buffer Size      */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS    16              /* max number of command args   */
+#define CFG_BARGSIZE   CFG_CBSIZE      /* Boot Argument Buffer Size    */
+
+#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+
+#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+
+#define CFG_MEMTEST_START      0x0400000       /* memtest works on     */
+#define CFG_MEMTEST_END                0x0C00000       /* 4 ... 12 MB in DRAM  */
+
+#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
+#define CFG_BASE_BAUD       691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE      \
+        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+         57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR  0x100000        /* default load address */
+#define CFG_EXTBDINFO  1               /* To use extended board_into (bd_t) */
+
+#define        CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK    /* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI                     /* include pci support          */
+#define CONFIG_PCI_HOST        PCI_HOST_AUTO   /* select pci host function     */
+#define CONFIG_PCI_PNP                 /* do pci plug-and-play         */
+                                        /* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
+#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
+#define CONFIG_IDE_RESET       1       /* reset for ide supported      */
+
+#define        CFG_IDE_MAXBUS          1               /* max. 1 IDE busses    */
+#define        CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define        CFG_ATA_BASE_ADDR       0xF0100000
+#define        CFG_ATA_IDE0_OFFSET     0x0000
+
+#define CFG_ATA_DATA_OFFSET    0x0000  /* Offset for data I/O                  */
+#define        CFG_ATA_REG_OFFSET      0x0000  /* Offset for normal register accesses  */
+#define CFG_ATA_ALT_OFFSET     0x0000  /* Offset for alternate registers       */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE         0x00000000
+#define CFG_FLASH_BASE         0xFFFD0000
+#define CFG_MONITOR_BASE       CFG_FLASH_BASE
+#define CFG_MONITOR_LEN                (192 * 1024)    /* Reserve 196 kB for Monitor   */
+#define CFG_MALLOC_LEN         (128 * 1024)    /* Reserve 128 kB for malloc()  */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ          (8 << 20)       /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS    2       /* max number of memory banks           */
+#define CFG_MAX_FLASH_SECT     256     /* max number of sectors on one chip    */
+
+#define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms)      */
+#define CFG_FLASH_WRITE_TOUT   500     /* Timeout for Flash Write (in ms)      */
+
+#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
+#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
+#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
+#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
+#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+
+#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+
+#if 0 /* Use NVRAM for environment variables */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_ENV_IS_IN_NVRAM    1       /* use NVRAM for environment vars       */
+#define CFG_ENV_SIZE           0x0ff8          /* Size of Environment vars     */
+#define CFG_ENV_ADDR           \
+       (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8))   /* Env  */  
+
+#else /* Use EEPROM for environment variables */
+
+#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE            0x800   /* 2048 bytes may be used for env vars*/
+                                   /* total size of a CAT24WC16 is 2048 bytes */
+#endif
+
+#define CFG_NVRAM_BASE_ADDR    0xf0200000              /* NVRAM base address   */
+#define CFG_NVRAM_SIZE         (32*1024)               /* NVRAM size           */
+#define CFG_NVRAM_VXWORKS_OFFS 0x6900          /* Offset for VxWorks eth-addr  */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C                        /* I2c with hardware support */
+#define CFG_I2C_SPEED          400000  /* I2C speed and slave address */
+#define CFG_I2C_SLAVE          0x7F
+
+#define CFG_I2C_EEPROM_ADDR    0x50    /* EEPROM CAT28WC08             */
+#define CFG_I2C_EEPROM_ADDR_LEN        1       /* Bytes of address             */
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW   0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4   /* The Catalyst CAT24WC08 has   */
+                                       /* 16 byte page write mode using*/
+                                       /* last 4 bits of the address   */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE 
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE                8192    /* For IBM 405 CPUs                     */
+#define CFG_CACHELINE_SIZE     32      /* ...                  */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM     0xFF800000      /* FLASH bank #0        */
+#define FLASH_BASE1_PRELIM     0xFFC00000      /* FLASH bank #1        */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization                                  */
+#define CFG_EBC_PB0AP           0x92015480
+#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1) initialization                                  */
+#define CFG_EBC_PB1AP           0x92015480
+#define CFG_EBC_PB1CR           0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (CAN0, 1) initialization                                       */
+#define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 3 (CompactFlash IDE) initialization                              */
+#define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (NVRAM/RTC) initialization                                     */
+#define CFG_EBC_PB4AP           0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1     */
+#define CFG_EBC_PB4CR           0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 5 (optional Quart) initialization                                */
+#define CFG_EBC_PB5AP           0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
+#define CFG_EBC_PB5CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 6 (FPGA internal) initialization                                 */
+#define CFG_EBC_PB6AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB6CR           0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CFG_FPGA_BASE_ADDR      0xF0400000
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+/* FPGA internal regs */
+#define CFG_FPGA_MODE           0x00
+#define CFG_FPGA_STATUS         0x02
+#define CFG_FPGA_TS             0x04
+#define CFG_FPGA_TS_LOW         0x06
+#define CFG_FPGA_TS_CAP0        0x08
+#define CFG_FPGA_TS_CAP0_LOW    0x0a
+#define CFG_FPGA_TS_CAP1        0x0c
+#define CFG_FPGA_TS_CAP1_LOW    0x0e
+
+/* FPGA Mode Reg */
+#define CFG_FPGA_MODE_CF_RESET  0x0001
+#define CFG_FPGA_MODE_IRQ_ENABLE 0x0100
+
+/* FPGA Status Reg */
+#define CFG_FPGA_STATUS_DIP0    0x0001
+#define CFG_FPGA_STATUS_DIP1    0x0002
+#define CFG_FPGA_STATUS_DIP2    0x0004
+#define CFG_FPGA_STATUS_FLASH   0x0008
+
+#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE       32*1024     /* 32kByte is enough for XC2S15  */
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+#if 1 /* test-only */
+#define CFG_INIT_DCACHE_CS      7       /* use cs # 7 for data cache memory    */
+
+#define CFG_INIT_RAM_ADDR       0x40000000  /* use data cache                  */
+#else
+#define CFG_INIT_RAM_ADDR      0x00df0000 /* inside of SDRAM                   */
+#endif
+#define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
+#define CFG_INIT_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_INIT_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET      CFG_INIT_DATA_OFFSET
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD  0x01            /* Normal Power-On: Boot from FLASH     */
+#define BOOTFLAG_WARM  0x02            /* Software reboot                      */
+
+#endif /* __CONFIG_H */

diff --git a/include/config_CPCIISER4.h b/include/config_CPCIISER4.h
index a7ec1d4313ea32d15cfe00e660e43e7c767b7bcb..5830a452249e49c3bb2b83a8b0c4ad50a0d21a21 100644 (file)
--- a/include/config_CPCIISER4.h
+++ b/include/config_CPCIISER4.h
@@ -166,12 +166,14 @@
 #define CFG_I2C_SLAVE          0x7F
 
 #define CFG_I2C_EEPROM_ADDR    0x50    /* EEPROM CAT28WC08             */
-#define CFG_I2C_EEPROM_ADDR_LEN        1       /* bytes of address             */
+#define CFG_I2C_EEPROM_ADDR_LEN        1       /* Bytes of address             */
 /* mask of address bits that overflow into the "EEPROM chip address"    */
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW   0x07
 #define CFG_EEPROM_PAGE_WRITE_BITS 4   /* The Catalyst CAT24WC08 has   */
                                        /* 16 byte page write mode using*/
                                        /* last 4 bits of the address   */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE 
 
 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 #define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */

diff --git a/include/config_DU405.h b/include/config_DU405.h
index 6b191a7ab3e73890eb50f6fd7456160de40d9d72..1e2ca733e37b75c32f23755bfebe24b34a7b5b58 100644 (file)
--- a/include/config_DU405.h
+++ b/include/config_DU405.h
@@ -191,13 +191,15 @@
 #define CFG_I2C_SPEED          400000  /* I2C speed and slave address */
 #define CFG_I2C_SLAVE          0x7F
 
-#define CFG_I2C_EEPROM_ADDR    0x50
-#define CFG_I2C_EEPROM_ADDR_LEN        1
+#define CFG_I2C_EEPROM_ADDR    0x50    /* EEPROM CAT28WC08             */
+#define CFG_I2C_EEPROM_ADDR_LEN        1       /* Bytes of address             */
 /* mask of address bits that overflow into the "EEPROM chip address"    */
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW   0x07
 #define CFG_EEPROM_PAGE_WRITE_BITS 4   /* The Catalyst CAT24WC08 has   */
                                        /* 16 byte page write mode using*/
                                        /* last 4 bits of the address   */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE 
 
 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 #define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */

diff --git a/include/config_OCRTC.h b/include/config_OCRTC.h
index 6d8a8429c41a7e3a8230851ff7cdb794e3825b3d..9f3bc5a261976e8440ae78c1bfee83fe5ad54574 100644 (file)
--- a/include/config_OCRTC.h
+++ b/include/config_OCRTC.h
@@ -201,6 +201,8 @@
 #define CFG_EEPROM_PAGE_WRITE_BITS 4   /* The Catalyst CAT24WC08 has   */
                                        /* 16 byte page write mode using*/
                                        /* last 4 bits of the address   */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE 
 
 /*-----------------------------------------------------------------------
  * Cache Configuration

diff --git a/include/config_ORSG.h b/include/config_ORSG.h
index 000b640a4ce5d222c44061c643b7e2b3a08160d0..b68e90f932557a6ae3e97990f8a6b8994e5e2fb6 100644 (file)
--- a/include/config_ORSG.h
+++ b/include/config_ORSG.h
@@ -201,6 +201,8 @@
 #define CFG_EEPROM_PAGE_WRITE_BITS 4   /* The Catalyst CAT24WC08 has   */
                                        /* 16 byte page write mode using*/
                                        /* last 4 bits of the address   */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE 
 
 /*-----------------------------------------------------------------------
  * Cache Configuration

diff --git a/include/config_OXC.h b/include/config_OXC.h
index 5b9aaa9a781d569e49cfc26e895e2567cd6428cf..4399bde8c16fb6d747f0f4351070c0a42de2320e 100644 (file)
--- a/include/config_OXC.h
+++ b/include/config_OXC.h
@@ -105,6 +105,7 @@
 #define CFG_FLASH0_BASE                0xFFF00000
 #define CFG_FLASH1_BASE                0xFFE00000
 #define CFG_FLASH_BASE         (0-flash_info[0].size)
+#define CFG_FLASH_PRELIMBASE   0xFF800000
 
 #define CFG_MAX_FLASH_BANKS    1       /* max number of memory banks           */
 #define CFG_MAX_FLASH_SECT     32      /* max number of sectors on one chip    */

diff --git a/include/config_ZUMA.h b/include/config_ZUMA.h
index 53efa16def74cc52b6115f3a06ba408613633bac..9f6434fb8ea5b149ef915dbf98a1a3b8573847a1 100644 (file)
--- a/include/config_ZUMA.h
+++ b/include/config_ZUMA.h
@@ -30,6 +30,10 @@
 
 #include <asm/processor.h>
 
+#define CFG_GT_6426x        GT_64260 /* with a 64260 system controller */
+#define CONFIG_ETHER_PORT_MII  /* use two MII ports */
+#define CONFIG_INTEL_LXT97X    /* Intel LXT97X phy */
+
 #ifndef __ASSEMBLY__
 #include <galileo/core.h>
 #endif
@@ -37,8 +41,9 @@
 #include "../board/evb64260/local.h"
 
 #define CONFIG_EVB64260                1       /* this is an EVB64260 board    */
-#define ZUMA_NTL               1       /* temporary, will rename to something nicer */
-#define CFG_GT_6426x        GT_64260 /* with a 64260 system controller */
+#define CONFIG_ZUMA_V2         1       /* always define this for ZUMA v2 */
+
+/* #define CONFIG_ZUMA_V2_OLD  1 */    /* backwards compat for old V2 board */
 
 #define CONFIG_BAUDRATE                38400   /* console baudrate = 38400     */
 
@@ -77,8 +82,6 @@
 /* define this if you want to enable GT MAC filtering */
 #define CONFIG_GT_USE_MAC_HASH_TABLE
  
-#define CONFIG_ETHER_PORT_MII  /* use MII */
-
 #if 1
 #define CONFIG_BOOTDELAY       -1      /* autoboot disabled            */
 #else
@@ -103,7 +106,8 @@
 #define CONFIG_BOOTP_MASK      (CONFIG_BOOTP_DEFAULT | \
                                 CONFIG_BOOTP_BOOTFILESIZE)
 
-#define CONFIG_MII
+#define CONFIG_MII             /* enable MII commands */
+
 #define CONFIG_COMMANDS                (CONFIG_CMD_DFL | \
                                 CFG_CMD_ASKENV | \
                                 CFG_CMD_BSP    | \
@@ -184,7 +188,7 @@
 #define CFG_GT_REGS            0xf8000000      /* later mapped GT_REGS */
 #define CFG_DEV_BASE           0xf0000000
 #define CFG_DEV0_SIZE          _64M /* zuma flash @ 0xf000.0000*/
-#define CFG_DEV1_SIZE           _8M /* unused */
+#define CFG_DEV1_SIZE           _8M /* zuma IDE   @ 0xf400.0000 */
 #define CFG_DEV2_SIZE           _8M /* unused */
 #define CFG_DEV3_SIZE           _8M /* unused */
 
@@ -195,30 +199,40 @@
        /* 11|00|0100|10 01|100|0 00|10 0|100 0|011 1|100 */
        /*  3| 0|.... ..| 1| 4 |  0 |  4 |   8 |   7 | 4  */
 
+#define CFG_DEV1_PAR           0xc01b6ac5
+       /*     c    0     1     b     6     a     c     5 */
+       /* 33 22|2222|22 22|111 1|11 11|1 1  |     |      */
+       /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
+       /* 11|00|0000|00 01|101|1 01|10 1|010 1|100 0|101 */
+       /*  3| 0|.... ..| 1| 5 |  5 |  5 |   5 |   8 | 5  */
+
+
+
 #define CFG_8BIT_BOOT_PAR      0xc00b5e7c
 
 #define CFG_MPP_CONTROL_0      0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */
 #define CFG_MPP_CONTROL_1      0x00000000 /* GPP[15:12] : GPP[11:8] */
 #define CFG_MPP_CONTROL_2      0x00008888 /* GPP[23:20] : REQ1[1:0] GNT1[1:0] */
-#define CFG_MPP_CONTROL_3      0x00009900 /* GPP[31:28] (pci int[3:0]) */
-                                          /* WDE WDNMI GPP[25:24] */
+#define CFG_MPP_CONTROL_3      0x00000000 /* GPP[31:28] (int[3:0]) */
+                                          /* GPP[27:24] (27 is int4, rest are GPP) */
 
 #define CFG_SERIAL_PORT_MUX    0x00001101 /* 11=MPSC1/MPSC0 01=ETH,  0=only MII */
-#define CFG_GPP_LEVEL_CONTROL  0xf000c000 /* GPP[31:28] ints GPP[15:14] led */
+#define CFG_GPP_LEVEL_CONTROL  0xf8000000 /* interrupt inputs: GPP[31:27] */
 
-#define CFG_SDRAM_CONFIG       0xf4e18200      /* 0x448 */
+#define CFG_SDRAM_CONFIG       0xe4e18200      /* 0x448 */
                                /* idmas use buffer 1,1
                                   comm use buffer 1
-                                  pci use buffer 1,0
+                                  pci use buffer 0,0 (pci1->0 pci0->0)
                                   cpu use buffer 1 (R*18)
                                   normal load (see also ifdef HVL)
                                   standard SDRAM (see also ifdef REG)
                                   non staggered refresh */
                                /* 31:26  25 23  20 19 18 16 */
-                               /* 111101 00 111 0  0  00 1 */
+                               /* 111001 00 111 0  0  00 1 */
 
                                /* refresh count=0x200
-                                  phy interleave disable (only one bank)
+                                  phy interleave disable (by default,
+                                  set later by dram config..)
                                   virt interleave enable */
                                /* 15 14 13:0 */
                                /* 1  0  0x200 */
@@ -260,17 +274,6 @@
 #define CFG_PCI1_IO_SPACE      (CFG_PCI1_IO_BASE)
 #define CFG_PCI1_IO_SPACE_PCI  0x00000000
 
-/*
- * NS16550 Configuration
- */
-#define CFG_NS16550
-
-#define CFG_NS16550_REG_SIZE   -4
-
-#define CFG_NS16550_CLK                3686400
-
-#define CFG_NS16550_COM1       (CFG_DUART_IO + 0)
-#define CFG_NS16550_COM2       (CFG_DUART_IO + 0x20)
 
 /*----------------------------------------------------------------------
  * Initial BAT mappings

diff --git a/include/galileo/core.h b/include/galileo/core.h
index 33033a38d723b10c29348aa4be673a88ba340ba9..56db09782aa6292b89b26ba860a9abc3c65f1978 100644 (file)
--- a/include/galileo/core.h
+++ b/include/galileo/core.h
@@ -24,7 +24,11 @@ extern unsigned int INTERNAL_REG_BASE_ADDR;
 #define GT_64261       1
 
 #if (CFG_GT_6426x == GT_64260)
+#ifdef CONFIG_ETHER_PORT_MII
+#define GAL_ETH_DEVS 2
+#else
 #define GAL_ETH_DEVS 3
+#endif
 #elif (CFG_GT_6426x == GT_64261)
 #define GAL_ETH_DEVS 2
 #else

diff --git a/include/ppcboot.h b/include/ppcboot.h
index 45dcf6c9d70d8fc089eaff1b1af235e8836f598a..627fd13a6606d2912e3ce92e111c64d66549fe7f 100644 (file)
--- a/include/ppcboot.h
+++ b/include/ppcboot.h
@@ -323,16 +323,16 @@ void  perform_soft_reset(void);
 void   load_sernum_ethaddr(bd_t *bd);
 #endif
 
-#if defined(CONFIG_CU824)      || \
+#if defined(CONFIG_BOARD_PRE_INIT) || \
+    defined(CONFIG_CU824)      || \
     defined(CONFIG_EP8260)     || \
+    defined(CONFIG_EVB64260)   || \
     defined(CONFIG_LWMON)      || \
-    defined(CONFIG_MIP405)     || \
     defined(CONFIG_MPC8260ADS) || \
-    defined(CONFIG_PIP405)     || \
+    defined(CONFIG_OXC)                || \
     defined(CONFIG_RPXSUPER)   || \
     defined(CONFIG_W7O)                || \
-    defined(CONFIG_WALNUT405)  || \
-    defined(CONFIG_BOARD_PRE_INIT)
+    defined(CONFIG_WALNUT405)
 /* $(BOARD)/$(BOARD).c */
 int    board_pre_init (void);
 #endif
@@ -410,23 +410,13 @@ ulong     get_tbclk     (void);
 #if defined(CONFIG_8260)
 void   get_8260_clks (void);
 void   prt_8260_clks (void);
-#elif defined(CONFIG_4xx)      || \
-      defined(CONFIG_8xx)      || \
-      defined(CONFIG_BAB750)   || \
-      defined(CONFIG_CU824)    || \
-      defined(CONFIG_EVB64260) || \
-      defined(CONFIG_IOP480)   || \
-      defined(CONFIG_MOUSSE)   || \
-      defined(CONFIG_MUSENKI)   || \
-      defined(CONFIG_SANDPOINT)
+#else
 ulong  get_gclk_freq (void);
-ulong  get_OPB_freq (void);
+#endif
 #ifdef CONFIG_4xx
+ulong  get_OPB_freq (void);
 ulong  get_PCI_freq (void);
 #endif
-#elif defined(CONFIG_74xx_7xx)
-ulong  get_gclk_freq (void);
-#endif
 
 ulong  get_bus_freq  (ulong);