arm64: dts: mediatek: mt8195: Reparent vdec1/2 and venc1 power domains

By hardware, the first and second core of the video decoder IP
need the VDEC_SOC to be powered up in order to be able to be
accessed (both internally, by firmware, and externally, by the
kernel).
Similarly, for the video encoder IP, the second core needs the
first core to be powered up in order to be accessible.

Fix that by reparenting the VDEC1/2 power domains to be children
of VDEC0 (VDEC_SOC), and the VENC1 to be a child of VENC0.

Fixes: 2b515194bf0c ("arm64: dts: mt8195: Add power domains controller")
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20250402090615.25871-3-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 4f2dc0a7556610907314184dea2a535e09d76ef0..1ded4b3f87605fbe46d58ffe388197c3fd36f846 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -617,22 +617,6 @@
                                        #size-cells = <0>;
                                        #power-domain-cells = <1>;
 
-                                       power-domain@MT8195_POWER_DOMAIN_VDEC1 {
-                                               reg = <MT8195_POWER_DOMAIN_VDEC1>;
-                                               clocks = <&vdecsys CLK_VDEC_LARB1>;
-                                               clock-names = "vdec1-0";
-                                               mediatek,infracfg = <&infracfg_ao>;
-                                               #power-domain-cells = <0>;
-                                       };
-
-                                       power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
-                                               reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
-                                               clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>;
-                                               clock-names = "venc1-larb";
-                                               mediatek,infracfg = <&infracfg_ao>;
-                                               #power-domain-cells = <0>;
-                                       };
-
                                        power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
                                                reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
                                                clocks = <&topckgen CLK_TOP_CFG_VDO0>,
@@ -678,15 +662,25 @@
                                                        clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
                                                        clock-names = "vdec0-0";
                                                        mediatek,infracfg = <&infracfg_ao>;
+                                                       #address-cells = <1>;
+                                                       #size-cells = <0>;
                                                        #power-domain-cells = <0>;
-                                               };
 
-                                               power-domain@MT8195_POWER_DOMAIN_VDEC2 {
-                                                       reg = <MT8195_POWER_DOMAIN_VDEC2>;
-                                                       clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
-                                                       clock-names = "vdec2-0";
-                                                       mediatek,infracfg = <&infracfg_ao>;
-                                                       #power-domain-cells = <0>;
+                                                       power-domain@MT8195_POWER_DOMAIN_VDEC1 {
+                                                               reg = <MT8195_POWER_DOMAIN_VDEC1>;
+                                                               clocks = <&vdecsys CLK_VDEC_LARB1>;
+                                                               clock-names = "vdec1-0";
+                                                               mediatek,infracfg = <&infracfg_ao>;
+                                                               #power-domain-cells = <0>;
+                                                       };
+
+                                                       power-domain@MT8195_POWER_DOMAIN_VDEC2 {
+                                                               reg = <MT8195_POWER_DOMAIN_VDEC2>;
+                                                               clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
+                                                               clock-names = "vdec2-0";
+                                                               mediatek,infracfg = <&infracfg_ao>;
+                                                               #power-domain-cells = <0>;
+                                                       };
                                                };
 
                                                power-domain@MT8195_POWER_DOMAIN_VENC {
@@ -694,7 +688,17 @@
                                                        clocks = <&vencsys CLK_VENC_LARB>;
                                                        clock-names = "venc0-larb";
                                                        mediatek,infracfg = <&infracfg_ao>;
+                                                       #address-cells = <1>;
+                                                       #size-cells = <0>;
                                                        #power-domain-cells = <0>;
+
+                                                       power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
+                                                               reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
+                                                               clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>;
+                                                               clock-names = "venc1-larb";
+                                                               mediatek,infracfg = <&infracfg_ao>;
+                                                               #power-domain-cells = <0>;
+                                                       };
                                                };
 
                                                power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {