arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node

Add dt node for the single instance of WIZ (SERDES wrapper) and
SERDES module shared by PCIe, eDP and USB.

Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230331090028.8373-3-r-gunasekaran@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 8d7b64728f882544458c8af68d9ec60c39f8e5b7..931263919086fccc1a9a39e180fff87f4d3c1e67 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -5,6 +5,17 @@
  * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
  */
 
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+       serdes_refclk: clock-cmnrefclk {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <0>;
+       };
+};
+
 &cbass_main {
        msmc_ram: sram@70000000 {
                compatible = "mmio-sram";
@@ -39,6 +50,14 @@
                        #mux-control-cells = <1>;
                        mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
                };
+
+               serdes_ln_ctrl: mux-controller@80 {
+                       compatible = "mmio-mux";
+                       reg = <0x80 0x10>;
+                       #mux-control-cells = <1>;
+                       mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
+                                       <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
+               };
        };
 
        gic500: interrupt-controller@1800000 {
@@ -790,6 +809,44 @@
                };
        };
 
+       serdes_wiz0: wiz@5060000 {
+               compatible = "ti,j721s2-wiz-10g";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
+               clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+               num-lanes = <4>;
+               #reset-cells = <1>;
+               #clock-cells = <1>;
+               ranges = <0x5060000 0x0 0x5060000 0x10000>;
+
+               assigned-clocks = <&k3_clks 365 3>;
+               assigned-clock-parents = <&k3_clks 365 7>;
+
+               serdes0: serdes@5060000 {
+                       compatible = "ti,j721e-serdes-10g";
+                       reg = <0x05060000 0x00010000>;
+                       reg-names = "torrent_phy";
+                       resets = <&serdes_wiz0 0>;
+                       reset-names = "torrent_reset";
+                       clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+                                <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+                       clock-names = "refclk", "phy_en_refclk";
+                       assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+                                         <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+                                         <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+                       assigned-clock-parents = <&k3_clks 365 3>,
+                                                <&k3_clks 365 3>,
+                                                <&k3_clks 365 3>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       #clock-cells = <1>;
+
+                       status = "disabled"; /* Needs lane config */
+               };
+       };
+
        main_mcan0: can@2701000 {
                compatible = "bosch,m_can";
                reg = <0x00 0x02701000 0x00 0x200>,