arm64/sve: Remove SMCR pseudo register from cpufeature code

For reasons that are not currently apparent during cpufeature enumeration
we maintain a pseudo register for SMCR which records the maximum supported
vector length using the value that would be written to SMCR_EL1.LEN to
configure it. This is not exposed to userspace and is not sufficient for
detecting unsupportable configurations, we need the more detailed checks in
vec_update_vq_map() for that since we can't cope with missing vector
lengths on late CPUs and KVM requires an exactly matching set of supported
vector lengths as EL1 can enumerate VLs directly with the hardware.

Remove the code, replacing the usage in sme_setup() with a query of the
vq_map.

Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230913-arm64-vec-len-cpufeature-v1-2-cc69b0600a8a@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
index f85650dc561c9cfeae5c10884a6e84ad45d3b798..f3034099fd952b204f45a683c84dd4e42dad0314 100644 (file)
--- a/arch/arm64/include/asm/cpu.h
+++ b/arch/arm64/include/asm/cpu.h
@@ -63,9 +63,6 @@ struct cpuinfo_arm64 {
        u64             reg_id_aa64smfr0;
 
        struct cpuinfo_32bit    aarch32;
-
-       /* pseudo-SMCR for recording maximum SMCR_EL1 LEN value: */
-       u64             reg_smcr;
 };
 
 DECLARE_PER_CPU(struct cpuinfo_arm64, cpu_data);

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 5783e93495635bf3cc69ee7a1a62b726859ff41f..ea36dc532b3b262a73ae5fd467bd874bd2e9d95b 100644 (file)
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -611,12 +611,6 @@ static const struct arm64_ftr_bits ftr_id_dfr1[] = {
        ARM64_FTR_END,
 };
 
-static const struct arm64_ftr_bits ftr_smcr[] = {
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
-               SMCR_ELx_LEN_SHIFT, SMCR_ELx_LEN_WIDTH, 0),     /* LEN */
-       ARM64_FTR_END,
-};
-
 /*
  * Common ftr bits for a 32bit register with all hidden, strict
  * attributes, with 4bit feature fields and a default safe value of
@@ -729,9 +723,6 @@ static const struct __ftr_reg_entry {
        ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
        ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3),
 
-       /* Op1 = 0, CRn = 1, CRm = 2 */
-       ARM64_FTR_REG(SYS_SMCR_EL1, ftr_smcr),
-
        /* Op1 = 1, CRn = 0, CRm = 0 */
        ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
 
@@ -1039,14 +1030,14 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
 
        if (IS_ENABLED(CONFIG_ARM64_SME) &&
            id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) {
-               info->reg_smcr = read_smcr_features();
+               sme_kernel_enable(NULL);
+
                /*
                 * We mask out SMPS since even if the hardware
                 * supports priorities the kernel does not at present
                 * and we block access to them.
                 */
                info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS;
-               init_cpu_ftr_reg(SYS_SMCR_EL1, info->reg_smcr);
                vec_init_vq_map(ARM64_VEC_SME);
        }
 
@@ -1292,15 +1283,14 @@ void update_cpu_features(int cpu,
 
        if (IS_ENABLED(CONFIG_ARM64_SME) &&
            id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) {
-               info->reg_smcr = read_smcr_features();
+               sme_kernel_enable(NULL);
+
                /*
                 * We mask out SMPS since even if the hardware
                 * supports priorities the kernel does not at present
                 * and we block access to them.
                 */
                info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS;
-               taint |= check_update_ftr_reg(SYS_SMCR_EL1, cpu,
-                                       info->reg_smcr, boot->reg_smcr);
 
                /* Probe vector lengths */
                if (!system_capabilities_finalized())
@@ -3152,19 +3142,11 @@ static void verify_sve_features(void)
 
 static void verify_sme_features(void)
 {
-       u64 safe_smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1);
-       u64 smcr = read_smcr_features();
-
-       unsigned int safe_len = safe_smcr & SMCR_ELx_LEN_MASK;
-       unsigned int len = smcr & SMCR_ELx_LEN_MASK;
-
-       if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SME)) {
+       if (vec_verify_vq_map(ARM64_VEC_SME)) {
                pr_crit("CPU%d: SME: vector length support mismatch\n",
                        smp_processor_id());
                cpu_die_early();
        }
-
-       /* Add checks on other SMCR bits here if necessary */
 }
 
 static void verify_hyp_capabilities(void)

diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index 35bf40c2f972fedb79899da77e82eeb1c3a3d72e..04c801001767b2cd36f97eab8cd2eac5584d76cf 100644 (file)
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -1304,32 +1304,10 @@ void fa64_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p)
                       SYS_SMCR_EL1);
 }
 
-/*
- * Read the pseudo-SMCR used by cpufeatures to identify the supported
- * vector length.
- *
- * Use only if SME is present.
- * This function clobbers the SME vector length.
- */
-u64 read_smcr_features(void)
-{
-       sme_kernel_enable(NULL);
-
-       /*
-        * Set the maximum possible VL.
-        */
-       write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_LEN_MASK,
-                      SYS_SMCR_EL1);
-
-       /* Return LEN value that would be written to get the maximum VL */
-       return sve_vq_from_vl(sme_get_vl()) - 1;
-}
-
 void __init sme_setup(void)
 {
        struct vl_info *info = &vl_info[ARM64_VEC_SME];
-       u64 smcr;
-       int min_bit;
+       int min_bit, max_bit;
 
        if (!system_supports_sme())
                return;
@@ -1338,24 +1316,16 @@ void __init sme_setup(void)
         * SME doesn't require any particular vector length be
         * supported but it does require at least one.  We should have
         * disabled the feature entirely while bringing up CPUs but
-        * let's double check here.
+        * let's double check here.  The bitmap is SVE_VQ_MAP sized for
+        * sharing with SVE.
         */
        WARN_ON(bitmap_empty(info->vq_map, SVE_VQ_MAX));
 
        min_bit = find_last_bit(info->vq_map, SVE_VQ_MAX);
        info->min_vl = sve_vl_from_vq(__bit_to_vq(min_bit));
 
-       smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1);
-       info->max_vl = sve_vl_from_vq((smcr & SMCR_ELx_LEN_MASK) + 1);
-
-       /*
-        * Sanity-check that the max VL we determined through CPU features
-        * corresponds properly to sme_vq_map.  If not, do our best:
-        */
-       if (WARN_ON(info->max_vl != find_supported_vector_length(ARM64_VEC_SME,
-                                                                info->max_vl)))
-               info->max_vl = find_supported_vector_length(ARM64_VEC_SME,
-                                                           info->max_vl);
+       max_bit = find_first_bit(info->vq_map, SVE_VQ_MAX);
+       info->max_vl = sve_vl_from_vq(__bit_to_vq(max_bit));
 
        WARN_ON(info->min_vl > info->max_vl);