drm/msm/a6xx: don't set IO_PGTABLE_QUIRK_ARM_OUTER_WBWA with coherent SMMU

If the Adreno SMMU is dma-coherent, allocation will fail unless we
disable IO_PGTABLE_QUIRK_ARM_OUTER_WBWA. Skip setting this quirk for the
coherent SMMUs (like we have on sm8350 platform).

Fixes: 54af0ceb7595 ("arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes")
Reported-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # SM8450 HDK
Patchwork: https://patchwork.freedesktop.org/patch/531562/
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 52da3795b175d0e9d9c0036bd9a2e050f7de973a..411b7a5fa2f329ec4e220bf3453a607f810ffa5d 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1744,7 +1744,8 @@ a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
         * This allows GPU to set the bus attributes required to use system
         * cache on behalf of the iommu page table walker.
         */
-       if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
+       if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice) &&
+           !device_iommu_capable(&pdev->dev, IOMMU_CAP_CACHE_COHERENCY))
                quirks |= IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
 
        return adreno_iommu_create_address_space(gpu, pdev, quirks);