void nvme_queue_async_events(struct nvme_ctrl *ctrl)
 {
-       ctrl->event_limit = NVME_NR_AERS;
+       ctrl->event_limit = NVME_NR_AEN_COMMANDS;
        queue_work(nvme_wq, &ctrl->async_event_work);
 }
 EXPORT_SYMBOL_GPL(nvme_queue_async_events);
 
 /* *************************** Data Structures/Defines ****************** */
 
 
-/*
- * We handle AEN commands ourselves and don't even let the
- * block layer know about them.
- */
-#define NVME_FC_NR_AEN_COMMANDS        1
-#define NVME_FC_AQ_BLKMQ_DEPTH \
-       (NVME_AQ_DEPTH - NVME_FC_NR_AEN_COMMANDS)
-#define AEN_CMDID_BASE         (NVME_FC_AQ_BLKMQ_DEPTH + 1)
-
 enum nvme_fc_queue_flags {
        NVME_FC_Q_CONNECTED = (1 << 0),
 };
        u32                     iocnt;
        wait_queue_head_t       ioabort_wait;
 
-       struct nvme_fc_fcp_op   aen_ops[NVME_FC_NR_AEN_COMMANDS];
+       struct nvme_fc_fcp_op   aen_ops[NVME_NR_AEN_COMMANDS];
 
        struct nvme_ctrl        ctrl;
 };
        unsigned long flags;
        int i, ret;
 
-       for (i = 0; i < NVME_FC_NR_AEN_COMMANDS; i++, aen_op++) {
+       for (i = 0; i < NVME_NR_AEN_COMMANDS; i++, aen_op++) {
                if (atomic_read(&aen_op->state) != FCPOP_STATE_ACTIVE)
                        continue;
 
        int i, ret;
 
        aen_op = ctrl->aen_ops;
-       for (i = 0; i < NVME_FC_NR_AEN_COMMANDS; i++, aen_op++) {
+       for (i = 0; i < NVME_NR_AEN_COMMANDS; i++, aen_op++) {
                private = kzalloc(ctrl->lport->ops->fcprqst_priv_sz,
                                                GFP_KERNEL);
                if (!private)
                sqe = &cmdiu->sqe;
                ret = __nvme_fc_init_request(ctrl, &ctrl->queues[0],
                                aen_op, (struct request *)NULL,
-                               (AEN_CMDID_BASE + i));
+                               (NVME_AQ_BLK_MQ_DEPTH + i));
                if (ret) {
                        kfree(private);
                        return ret;
                memset(sqe, 0, sizeof(*sqe));
                sqe->common.opcode = nvme_admin_async_event;
                /* Note: core layer may overwrite the sqe.command_id value */
-               sqe->common.command_id = AEN_CMDID_BASE + i;
+               sqe->common.command_id = NVME_AQ_BLK_MQ_DEPTH + i;
        }
        return 0;
 }
        int i;
 
        aen_op = ctrl->aen_ops;
-       for (i = 0; i < NVME_FC_NR_AEN_COMMANDS; i++, aen_op++) {
+       for (i = 0; i < NVME_NR_AEN_COMMANDS; i++, aen_op++) {
                if (!aen_op->fcp_req.private)
                        continue;
 
        bool terminating = false;
        blk_status_t ret;
 
-       if (aer_idx > NVME_FC_NR_AEN_COMMANDS)
+       if (aer_idx > NVME_NR_AEN_COMMANDS)
                return;
 
        spin_lock_irqsave(&ctrl->lock, flags);
         * Create the admin queue
         */
 
-       nvme_fc_init_queue(ctrl, 0, NVME_FC_AQ_BLKMQ_DEPTH);
+       nvme_fc_init_queue(ctrl, 0, NVME_AQ_BLK_MQ_DEPTH);
 
        ret = __nvme_fc_create_hw_queue(ctrl, &ctrl->queues[0], 0,
-                               NVME_FC_AQ_BLKMQ_DEPTH);
+                               NVME_AQ_BLK_MQ_DEPTH);
        if (ret)
                goto out_free_queue;
 
        ret = nvme_fc_connect_admin_queue(ctrl, &ctrl->queues[0],
-                               NVME_FC_AQ_BLKMQ_DEPTH,
-                               (NVME_FC_AQ_BLKMQ_DEPTH / 4));
+                               NVME_AQ_BLK_MQ_DEPTH,
+                               (NVME_AQ_BLK_MQ_DEPTH / 4));
        if (ret)
                goto out_delete_hw_queue;
 
 
        memset(&ctrl->admin_tag_set, 0, sizeof(ctrl->admin_tag_set));
        ctrl->admin_tag_set.ops = &nvme_fc_admin_mq_ops;
-       ctrl->admin_tag_set.queue_depth = NVME_FC_AQ_BLKMQ_DEPTH;
+       ctrl->admin_tag_set.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
        ctrl->admin_tag_set.reserved_tags = 2; /* fabric connect + Keep-Alive */
        ctrl->admin_tag_set.numa_node = NUMA_NO_NODE;
        ctrl->admin_tag_set.cmd_size = sizeof(struct nvme_fc_fcp_op) +
 
 int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
                bool send);
 
-#define NVME_NR_AERS   1
 void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
                union nvme_result *res);
 void nvme_queue_async_events(struct nvme_ctrl *ctrl);
 
 #define SQ_SIZE(depth)         (depth * sizeof(struct nvme_command))
 #define CQ_SIZE(depth)         (depth * sizeof(struct nvme_completion))
 
-/*
- * We handle AEN commands ourselves and don't even let the
- * block layer know about them.
- */
-#define NVME_AQ_BLKMQ_DEPTH    (NVME_AQ_DEPTH - NVME_NR_AERS)
-
 #define SGES_PER_PAGE  (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
 
 static int use_threaded_interrupts;
         * for them but rather special case them here.
         */
        if (unlikely(nvmeq->qid == 0 &&
-                       cqe->command_id >= NVME_AQ_BLKMQ_DEPTH)) {
+                       cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
                nvme_complete_async_event(&nvmeq->dev->ctrl,
                                cqe->status, &cqe->result);
                return;
 
        memset(&c, 0, sizeof(c));
        c.common.opcode = nvme_admin_async_event;
-       c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
+       c.common.command_id = NVME_AQ_BLK_MQ_DEPTH + aer_idx;
 
        spin_lock_irq(&nvmeq->q_lock);
        __nvme_submit_cmd(nvmeq, &c);
                dev->admin_tagset.ops = &nvme_mq_admin_ops;
                dev->admin_tagset.nr_hw_queues = 1;
 
-               /*
-                * Subtract one to leave an empty queue entry for 'Full Queue'
-                * condition. See NVM-Express 1.2 specification, section 4.1.2.
-                */
-               dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
+               dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
                dev->admin_tagset.timeout = ADMIN_TIMEOUT;
                dev->admin_tagset.numa_node = dev_to_node(dev->dev);
                dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
 
 
 #define NVME_RDMA_MAX_INLINE_SEGMENTS  1
 
-/*
- * We handle AEN commands ourselves and don't even let the
- * block layer know about them.
- */
-#define NVME_RDMA_NR_AEN_COMMANDS      1
-#define NVME_RDMA_AQ_BLKMQ_DEPTH       \
-       (NVME_AQ_DEPTH - NVME_RDMA_NR_AEN_COMMANDS)
-
 struct nvme_rdma_device {
        struct ib_device        *dev;
        struct ib_pd            *pd;
                set = &ctrl->admin_tag_set;
                memset(set, 0, sizeof(*set));
                set->ops = &nvme_rdma_admin_mq_ops;
-               set->queue_depth = NVME_RDMA_AQ_BLKMQ_DEPTH;
+               set->queue_depth = NVME_AQ_MQ_TAG_DEPTH;
                set->reserved_tags = 2; /* connect + keep-alive */
                set->numa_node = NUMA_NO_NODE;
                set->cmd_size = sizeof(struct nvme_rdma_request) +
 
        memset(cmd, 0, sizeof(*cmd));
        cmd->common.opcode = nvme_admin_async_event;
-       cmd->common.command_id = NVME_RDMA_AQ_BLKMQ_DEPTH;
+       cmd->common.command_id = NVME_AQ_BLK_MQ_DEPTH;
        cmd->common.flags |= NVME_CMD_SGL_METABUF;
        nvme_rdma_set_sg_null(cmd);
 
         * for them but rather special case them here.
         */
        if (unlikely(nvme_rdma_queue_idx(queue) == 0 &&
-                       cqe->command_id >= NVME_RDMA_AQ_BLKMQ_DEPTH))
+                       cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH))
                nvme_complete_async_event(&queue->ctrl->ctrl, cqe->status,
                                &cqe->result);
        else
 
 
 #define NVME_LOOP_MAX_SEGMENTS         256
 
-/*
- * We handle AEN commands ourselves and don't even let the
- * block layer know about them.
- */
-#define NVME_LOOP_NR_AEN_COMMANDS      1
-#define NVME_LOOP_AQ_BLKMQ_DEPTH       \
-       (NVME_AQ_DEPTH - NVME_LOOP_NR_AEN_COMMANDS)
-
 struct nvme_loop_iod {
        struct nvme_request     nvme_req;
        struct nvme_command     cmd;
         * for them but rather special case them here.
         */
        if (unlikely(nvme_loop_queue_idx(queue) == 0 &&
-                       cqe->command_id >= NVME_LOOP_AQ_BLKMQ_DEPTH)) {
+                       cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
                nvme_complete_async_event(&queue->ctrl->ctrl, cqe->status,
                                &cqe->result);
        } else {
 
        memset(&iod->cmd, 0, sizeof(iod->cmd));
        iod->cmd.common.opcode = nvme_admin_async_event;
-       iod->cmd.common.command_id = NVME_LOOP_AQ_BLKMQ_DEPTH;
+       iod->cmd.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
        iod->cmd.common.flags |= NVME_CMD_SGL_METABUF;
 
        if (!nvmet_req_init(&iod->req, &queue->nvme_cq, &queue->nvme_sq,
 
        memset(&ctrl->admin_tag_set, 0, sizeof(ctrl->admin_tag_set));
        ctrl->admin_tag_set.ops = &nvme_loop_admin_mq_ops;
-       ctrl->admin_tag_set.queue_depth = NVME_LOOP_AQ_BLKMQ_DEPTH;
+       ctrl->admin_tag_set.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
        ctrl->admin_tag_set.reserved_tags = 2; /* connect + keep-alive */
        ctrl->admin_tag_set.numa_node = NUMA_NO_NODE;
        ctrl->admin_tag_set.cmd_size = sizeof(struct nvme_loop_iod) +
 
 };
 
 #define NVME_AQ_DEPTH          32
+#define NVME_NR_AEN_COMMANDS   1
+#define NVME_AQ_BLK_MQ_DEPTH   (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
+
+/*
+ * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
+ * NVM-Express 1.2 specification, section 4.1.2.
+ */
+#define NVME_AQ_MQ_TAG_DEPTH   (NVME_AQ_BLK_MQ_DEPTH - 1)
 
 enum {
        NVME_REG_CAP    = 0x0000,       /* Controller Capabilities */