Merge tag 'drm-intel-next-2023-09-29' of git://anongit.freedesktop.org/drm/drm-intel...

drm/i915 feature pull for v6.7:

Features and functionality:
- Early Xe2 LPD / Lunarlake (LNL) display enabling (Lucas, Matt, Gustavo,
  Stanislav, Luca, Clint, Juha-Pekka, Balasubramani, Ravi)
- Plenty of various DSC improvements and fixes (Ankit)
- Add DSC PPS state readout and verification (Suraj)
- Improve fastsets for VRR, LRR and M/N updates (Ville)
- Use connector->ddc to create (non-DP MST) connector sysfs ddc symlinks (Ville)
- Various DSB improvements, load LUTs using DSB (Ville)
- Improve shared link bandwidth management, starting with FDI (Imre)
- Optimize get param ioctl for PXP status (Alan)
- Remove DG2 pre-production hardware workarounds (Matt)
- Add more RPL P/U PCI IDs (Dnyaneshwar)
- Add new DG2-G12 stepping (Swati)
- Add PSR sink error status to debugfs (Jouni)
- Add DP enhanced framing to crtc state checker (Ville)

Refactoring and cleanups:
- Simplify TileY/Tile4 tiling selftest enumeration (Matt)
- Remove some unused power domain code (Gustavo)
- Check stepping of display IP version rather than MTL platform (Matt)
- DP audio compute config cleanups (Vinod)
- SDVO cleanups and refactoring, more robust failure handling (Ville)
- Color register definition and readout cleanups (Jani)
- Reduce header interdependencies for frontbuffer tracking (Jani)
- Continue replacing struct edid with struct drm_edid (Jani)
- Use source physical address instead of EDID for CEC (Jani)
- Clean up Type-C port lane count functions (Luca)
- Clean up DSC PPS register definitions and readout (Jani)
- Stop using GEM_BUG_ON()/GEM_WARN_ON() in display code (Jani)
- Move more of the display probe to display code (Jani)
- Remove redundant runtime suspended state flag (Jouni)
- Move display info printing to display code (Balasubramani)
- Frontbuffer tracking improvements (Jouni)
- Add trailing newlines to debug logging (Jim Cromie)
- Separate display workarounds from clock gating init (Matt)
- Reduce dmesg log spamming for combo PHY, PLL state, FEC, DP MST (Ville, Imre)

Fixes:
- Fix hotplug poll detect loops via suspend/resume (Imre)
- Fix hotplug detect for forced connectors (Imre)
- Fix DSC first_line_bpg_offset calculation (Suraj)
- Fix debug prints for SDP CRC16 (Arun)
- Fix PXP runtime resume (Alan)
- Fix cx0 PHY lane handling (Gustavo)
- Fix frontbuffer tracking locking in debugfs (Juha-Pekka)
- Fix SDVO detect on some models (Ville)
- Fix SDP split configuration for DP MST (Vinod)
- Fix AUX usage and reads for HDCP on DP MST (Suraj)
- Fix PSR workaround (Jouni)
- Fix redundant AUX power get/put in DP force (Imre)
- Fix ICL DSI TCLK POST by letting hardware handle it (William)
- Fix IRQ reset for XE LP+ (Gustavo)
- Fix h/vsync_end instead of h/vtotal in VBT (Ville)
- Fix C20 PHY msgbus timeout issues (Gustavo)
- Fix pre-TGL FEC pipe A vs. DDI A mixup (Ville)
- Fix FEC state readout for DP MST (Ville)

DRM subsystem core changes:
- Assume sink supports 8 bpc when DSC is supported (Ankit)
- Add drm_edid_is_digital() helper (Jani)
- Parse source physical address from EDID (Jani)
- Add function to attach CEC without EDID (Jani)
- Reorder connector sysfs/debugfs remove (Ville)
- Register connector sysfs ddc symlink later (Ville)

Media subsystem changes:
- Add comments about CEC source physical address usage (Jani)

Merges:
- Backmerge drm-next to get v6.6-rc1 (Jani)

Signed-off-by: Dave Airlie <airlied@redhat.com>
# Conflicts:
#	drivers/gpu/drm/i915/i915_drv.h
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87r0mhi7a6.fsf@intel.com

diff --cc drivers/gpu/drm/drm_connector.c
Simple merge

diff --cc drivers/gpu/drm/drm_edid.c
Simple merge

diff --cc drivers/gpu/drm/drm_internal.h
Simple merge

diff --cc drivers/gpu/drm/i915/display/intel_dp_mst.c
Simple merge

diff --cc drivers/gpu/drm/i915/display/skl_universal_plane.c
Simple merge

diff --cc drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_drv.h
index ea92a00353daf502c73b71463e06a289a1ca6c23,cc229f08dfdb9b4cd1f23c8a042eb96fd49f4f05..511eba3bbdbae1a958c7b30a93b0d26c372283a6
--- 1/drivers/gpu/drm/i915/i915_drv.h
--- 2/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@@ -647,21 -653,33 +649,6 @@@ IS_SUBPLATFORM(const struct drm_i915_pr
  #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
        (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
  
- #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
 -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
 -      (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
 -       IS_GRAPHICS_STEP(__i915, since, until))
 -
 -#define IS_MTL_MEDIA_STEP(__i915, since, until) \
--      (IS_METEORLAKE(__i915) && \
-        IS_DISPLAY_STEP(__i915, since, until))
 -       IS_MEDIA_STEP(__i915, since, until))
--
- #define IS_DG2_DISPLAY_STEP(__i915, since, until) \
-       (IS_DG2(__i915) && \
-        IS_DISPLAY_STEP(__i915, since, until))
 -/*
 - * DG2 hardware steppings are a bit unusual.  The hardware design was forked to
 - * create three variants (G10, G11, and G12) which each have distinct
 - * workaround sets.  The G11 and G12 forks of the DG2 design reset the GT
 - * stepping back to "A0" for their first iterations, even though they're more
 - * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of
 - * functionality and workarounds.  However the display stepping does not reset
 - * in the same manner --- a specific stepping like "B0" has a consistent
 - * meaning regardless of whether it belongs to a G10, G11, or G12 DG2.
 - *
 - * TLDR:  All GT workarounds and stepping-specific logic must be applied in
 - * relation to a specific subplatform (G10/G11/G12), whereas display workarounds
 - * and stepping-specific logic will be applied with a general DG2-wide stepping
 - * number.
 - */
 -#define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \
 -      (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
 -       IS_GRAPHICS_STEP(__i915, since, until))
--
  #define IS_PVC_BD_STEP(__i915, since, until) \
        (IS_PONTEVECCHIO(__i915) && \
         IS_BASEDIE_STEP(__i915, since, until))

diff --cc drivers/gpu/drm/i915/intel_clock_gating.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_device_info.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_device_info.h
Simple merge

diff --cc drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
Simple merge

diff --cc drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
Simple merge

diff --cc include/drm/drm_connector.h
Simple merge

diff --cc include/drm/i915_pciids.h
Simple merge