return false;
 }
 
-static void radeon_dp_set_panel_mode(struct drm_encoder *encoder,
-                                    struct drm_connector *connector)
+int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
+                            struct drm_connector *connector)
 {
        struct drm_device *dev = encoder->dev;
        struct radeon_device *rdev = dev->dev_private;
        int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 
        if (!ASIC_IS_DCE4(rdev))
-               return;
+               return panel_mode;
 
        if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
            ENCODER_OBJECT_ID_NUTMEG)
                        panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
        }
 
-       atombios_dig_encoder_setup(encoder,
-                                  ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
-                                  panel_mode);
-
-       if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
-           (panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
-               radeon_write_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_SET, 1);
-       }
+       return panel_mode;
 }
 
 void radeon_dp_set_link_config(struct drm_connector *connector,
 
 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
 {
+       struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
+       struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
        u8 tmp;
 
        /* power up the sink */
                radeon_write_dpcd_reg(dp_info->radeon_connector,
                                      DP_DOWNSPREAD_CTRL, 0);
 
-       radeon_dp_set_panel_mode(dp_info->encoder, dp_info->connector);
+       if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
+           (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
+               radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1);
+       }
 
        /* set the lane count on the sink */
        tmp = dp_info->dp_lane_count;
 
        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
                if (ASIC_IS_DCE4(rdev)) {
+                       struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
+                       struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
+
+                       if (!connector)
+                               dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
+                       else
+                               dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
+
                        /* disable the transmitter */
                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
                        /* setup and enable the encoder */
                        atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
+                       atombios_dig_encoder_setup(encoder,
+                                                  ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
+                                                  dig->panel_mode);
 
                        /* enable the transmitter */
                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
 
        struct backlight_device *bl_dev;
        int dpms_mode;
        uint8_t backlight_level;
+       int panel_mode;
 };
 
 struct radeon_encoder_atom_dac {
 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
+extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
+                                   struct drm_connector *connector);
 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
 extern void radeon_atom_encoder_init(struct radeon_device *rdev);
 extern void radeon_atom_dcpll_init(struct radeon_device *rdev);