drm/amd/display: Remove unnecessary code

This commit groups many parts of the code that are redundant or not used
and drops all of them.

Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 9475dab39af505a18d0f586dcc75691015b2a46b..110e2dc884b229f250cd86f6f41aadc9ae9805ad 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1006,7 +1006,6 @@ struct dc_debug_options {
        unsigned int force_cositing;
 };
 
-struct gpu_info_soc_bounding_box_v1_0;
 
 /* Generic structure that can be used to query properties of DC. More fields
  * can be added as required.

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index 744c335718a7b9a53ab685b25131065f594e093a..ee601a6897a14dd2950d35d9bd2365cabd44a5f6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -312,9 +312,6 @@ static bool setup_engine(
        /* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/
        REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);
 
-       /* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/
-       REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);
-
        /*set SW requested I2c speed to default, if API calls in it will be override later*/
        set_speed(dce_i2c_hw, dce_i2c_hw->ctx->dc->caps.i2c_speed_in_khz);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index d980e6bd6c6647a6264c051ff3679fedd7e415b2..b7a89c39f4459f3a28921a4ef6bbddb66fe02019 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -167,7 +167,6 @@ struct dcn10_link_enc_registers {
        uint32_t DIO_LINKD_CNTL;
        uint32_t DIO_LINKE_CNTL;
        uint32_t DIO_LINKF_CNTL;
-       uint32_t DIG_FIFO_CTRL0;
        uint32_t DIO_CLK_CNTL;
        uint32_t DIG_BE_CLK_CNTL;
 };
@@ -475,9 +474,6 @@ struct dcn10_link_enc_registers {
        type HPO_DP_ENC_SEL;\
        type HPO_HDMI_ENC_SEL
 
-#define DCN32_LINK_ENCODER_REG_FIELD_LIST(type) \
-       type DIG_FIFO_OUTPUT_PIXEL_MODE
-
 #define DCN35_LINK_ENCODER_REG_FIELD_LIST(type) \
        type DIG_BE_ENABLE;\
        type DIG_RB_SWITCH_EN;\
@@ -512,7 +508,6 @@ struct dcn10_link_enc_shift {
        DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
        DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
        DCN31_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
-       DCN32_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
        DCN35_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 };
 
@@ -521,7 +516,6 @@ struct dcn10_link_enc_mask {
        DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
        DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
        DCN31_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
-       DCN32_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
        DCN35_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h
index 35a613bb08bf3cbff1d89d0fdca470b6fab7059e..08a57ea4591c6d28f178987ed271d83cf6bc88a3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h
@@ -29,13 +29,6 @@
 #include "dcn20/dcn20_dccg.h"
 
 
-#define DCCG_REG_LIST_DCN3AG() \
-       DCCG_COMMON_REG_LIST_DCN_BASE(),\
-       SR(PHYASYMCLK_CLOCK_CNTL),\
-       SR(PHYBSYMCLK_CLOCK_CNTL),\
-       SR(PHYCSYMCLK_CLOCK_CNTL)
-
-
 #define DCCG_REG_LIST_DCN30() \
        DCCG_REG_LIST_DCN2(),\
        DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
@@ -46,17 +39,6 @@
        SR(PHYBSYMCLK_CLOCK_CNTL),\
        SR(PHYCSYMCLK_CLOCK_CNTL)
 
-#define DCCG_MASK_SH_LIST_DCN3AG(mask_sh) \
-       DCCG_MASK_SH_LIST_DCN2_1(mask_sh),\
-       DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\
-       DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\
-       DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
-       DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
-       DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
-       DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
-       DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
-       DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh)
-
 #define DCCG_MASK_SH_LIST_DCN3(mask_sh) \
        DCCG_MASK_SH_LIST_DCN2(mask_sh),\
        DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c
index 1b9d9495f76de939be2eea742ba611341170ad8d..fae98cf520201d5afe11c8c17e57d0a5c6dc1a9e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c
@@ -251,9 +251,7 @@ static const struct dwbc_funcs dcn30_dwbc_funcs = {
        .set_fc_enable          = dwb3_set_fc_enable,
        .set_stereo             = dwb3_set_stereo,
        .set_new_content        = dwb3_set_new_content,
-       .dwb_program_output_csc = NULL,
        .dwb_ogam_set_input_transfer_func       = dwb3_ogam_set_input_transfer_func, //TODO: rename
-       .dwb_set_scaler         = NULL,
 };
 
 void dcn30_dwbc_construct(struct dcn30_dwbc *dwbc30,