drm/amdgpu: enable ras eeprom support for sienna cichlid

added I2C address and asic support flag

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index 1dd040166c635e2dc1bd0bfa30c255a847a9c5da..19d9aa76cfbfbca0db3a66f29197ba4fbaae5ced 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
@@ -30,6 +30,7 @@
 #define EEPROM_I2C_TARGET_ADDR_VEGA20          0xA0
 #define EEPROM_I2C_TARGET_ADDR_ARCTURUS                0xA8
 #define EEPROM_I2C_TARGET_ADDR_ARCTURUS_D342   0xA0
+#define EEPROM_I2C_TARGET_ADDR_SIENNA_CICHLID   0xA0
 
 /*
  * The 2 macros bellow represent the actual size in bytes that
@@ -62,7 +63,8 @@
 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev)
 {
        if ((adev->asic_type == CHIP_VEGA20) ||
-           (adev->asic_type == CHIP_ARCTURUS))
+           (adev->asic_type == CHIP_ARCTURUS) ||
+           (adev->asic_type == CHIP_SIENNA_CICHLID))
                return true;
 
        return false;
@@ -100,6 +102,10 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
        case CHIP_ARCTURUS:
                return __get_eeprom_i2c_addr_arct(adev, i2c_addr);
 
+       case CHIP_SIENNA_CICHLID:
+               *i2c_addr = EEPROM_I2C_TARGET_ADDR_SIENNA_CICHLID;
+               break;
+
        default:
                return false;
        }