unsigned long tmio_flags;
        unsigned long capabilities;
        unsigned long capabilities2;
+       dma_addr_t dma_rx_offset;
 };
 
 static const struct sh_mobile_sdhi_of_data sh_mobile_sdhi_of_cfg[] = {
        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE,
        .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
        .capabilities2  = MMC_CAP2_NO_MULTI_READ,
+       .dma_rx_offset  = 0x2000,
 };
 
 static const struct of_device_id sh_mobile_sdhi_of_match[] = {
                mmc_data->flags |= of_data->tmio_flags;
                mmc_data->capabilities |= of_data->capabilities;
                mmc_data->capabilities2 |= of_data->capabilities2;
+               dma_priv->dma_rx_offset = of_data->dma_rx_offset;
        }
 
        /* SD control register space size is 0x100, 0x200 for bus_shift=1 */
 
                if (pdata->dma->chan_priv_rx)
                        cfg.slave_id = pdata->dma->slave_id_rx;
                cfg.direction = DMA_DEV_TO_MEM;
-               cfg.src_addr = cfg.dst_addr;
+               cfg.src_addr = cfg.dst_addr + pdata->dma->dma_rx_offset;
                cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
                cfg.dst_addr = 0;
                ret = dmaengine_slave_config(host->chan_rx, &cfg);