u32 q_depth;
        u16 cq_vector;
        u16 sq_tail;
+       u16 last_sq_tail;
        u16 cq_head;
        u16 qid;
        u8 cq_phase;
        return 0;
 }
 
-static inline void nvme_write_sq_db(struct nvme_queue *nvmeq)
+/*
+ * Write sq tail if we are asked to, or if the next command would wrap.
+ */
+static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
 {
+       if (!write_sq) {
+               u16 next_tail = nvmeq->sq_tail + 1;
+
+               if (next_tail == nvmeq->q_depth)
+                       next_tail = 0;
+               if (next_tail != nvmeq->last_sq_tail)
+                       return;
+       }
+
        if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
                        nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
                writel(nvmeq->sq_tail, nvmeq->q_db);
+       nvmeq->last_sq_tail = nvmeq->sq_tail;
 }
 
 /**
               cmd, sizeof(*cmd));
        if (++nvmeq->sq_tail == nvmeq->q_depth)
                nvmeq->sq_tail = 0;
-       if (write_sq)
-               nvme_write_sq_db(nvmeq);
+       nvme_write_sq_db(nvmeq, write_sq);
        spin_unlock(&nvmeq->sq_lock);
 }
 
        struct nvme_queue *nvmeq = hctx->driver_data;
 
        spin_lock(&nvmeq->sq_lock);
-       nvme_write_sq_db(nvmeq);
+       if (nvmeq->sq_tail != nvmeq->last_sq_tail)
+               nvme_write_sq_db(nvmeq, true);
        spin_unlock(&nvmeq->sq_lock);
 }
 
        struct nvme_dev *dev = nvmeq->dev;
 
        nvmeq->sq_tail = 0;
+       nvmeq->last_sq_tail = 0;
        nvmeq->cq_head = 0;
        nvmeq->cq_phase = 1;
        nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];