ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
        ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
        ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
-       ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
        ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
-       ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
 
        return 0;
 #undef ATH_ALLOC_BANK
        u32 ob5GHz = 0, db5GHz = 0;
        u32 ob2GHz = 0, db2GHz = 0;
        int regWrites = 0;
+       int i;
 
        /*
         * Software does not need to program bank data
        /* Setup Bank 6 Write */
        ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3,
                      modesIndex);
-       {
-               int i;
-               for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
-                       ah->analogBank6Data[i] =
-                           INI_RA(&ah->iniBank6TPC, i, modesIndex);
-               }
-       }
+
+       for (i = 0; i < ah->iniBank6.ia_rows; i++)
+               ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex);
 
        /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
        if (eepMinorRev >= 2) {
        ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1);
 
        /* Write Analog registers */
-       REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
-                          regWrites);
-       REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
-                          regWrites);
-       REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
-                          regWrites);
-       REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
-                          regWrites);
-       REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
-                          regWrites);
-       REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
-                          regWrites);
+       REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data, regWrites);
+       REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data, regWrites);
+       REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data, regWrites);
+       REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data, regWrites);
+       REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, regWrites);
+       REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data, regWrites);
 
        return true;
 }
 
        } else if (AR_SREV_9100_OR_LATER(ah)) {
                INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100);
                INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100);
-               INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100);
                INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100);
        } else {
                INIT_INI_ARRAY(&ah->iniModes, ar5416Modes);
                INIT_INI_ARRAY(&ah->iniCommon, ar5416Common);
-               INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC);
                INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac);
        }
 
                INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3);
                INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7);
 
-               /* Common for AR5416, AR9160 */
-               if (!AR_SREV_9100(ah))
-                       INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6);
-
                /* Common for AR913x, AR9160 */
                if (!AR_SREV_5416(ah))
-                       INIT_INI_ARRAY(&ah->iniBank6TPC,
-                                     ar5416Bank6TPC_9100);
+                       INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC_9100);
+               else
+                       INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC);
        }
 
        /* iniAddac needs to be modified for these chips */