return true;
 }
 
-static int mid_spi_dma_init(struct dw_spi *dws)
+static int mid_spi_dma_init_mfld(struct dw_spi *dws)
 {
        struct pci_dev *dma_dev;
        struct dw_dma_slave *tx = dws->dma_tx;
        }
 }
 
-static const struct dw_spi_dma_ops mid_dma_ops = {
-       .dma_init       = mid_spi_dma_init,
+static const struct dw_spi_dma_ops mfld_dma_ops = {
+       .dma_init       = mid_spi_dma_init_mfld,
        .dma_exit       = mid_spi_dma_exit,
        .dma_setup      = mid_spi_dma_setup,
        .can_dma        = mid_spi_can_dma,
        .dma_transfer   = mid_spi_dma_transfer,
        .dma_stop       = mid_spi_dma_stop,
 };
+
+static void dw_spi_mid_setup_dma_mfld(struct dw_spi *dws)
+{
+       dws->dma_tx = &mid_dma_tx;
+       dws->dma_rx = &mid_dma_rx;
+       dws->dma_ops = &mfld_dma_ops;
+}
+#else  /* CONFIG_SPI_DW_MID_DMA */
+static inline void dw_spi_mid_setup_dma_mfld(struct dw_spi *dws) {}
 #endif
 
 /* Some specific info for SPI0 controller on Intel MID */
 #define CLK_SPI_CDIV_MASK      0x00000e00
 #define CLK_SPI_DISABLE_OFFSET 8
 
-int dw_spi_mid_init(struct dw_spi *dws)
+int dw_spi_mid_init_mfld(struct dw_spi *dws)
 {
        void __iomem *clk_reg;
        u32 clk_cdiv;
 
        iounmap(clk_reg);
 
-#ifdef CONFIG_SPI_DW_MID_DMA
-       dws->dma_tx = &mid_dma_tx;
-       dws->dma_rx = &mid_dma_rx;
-       dws->dma_ops = &mid_dma_ops;
-#endif
-
        /* Register hook to configure CTRLR0 */
        dws->update_cr0 = dw_spi_update_cr0;
 
+       dw_spi_mid_setup_dma_mfld(dws);
        return 0;
 }
 
 };
 
 static struct spi_pci_desc spi_pci_mid_desc_1 = {
-       .setup = dw_spi_mid_init,
+       .setup = dw_spi_mid_init_mfld,
        .num_cs = 5,
        .bus_num = 0,
 };
 
 static struct spi_pci_desc spi_pci_mid_desc_2 = {
-       .setup = dw_spi_mid_init,
+       .setup = dw_spi_mid_init_mfld,
        .num_cs = 2,
        .bus_num = 1,
 };