]> www.infradead.org Git - linux-platform-drivers-x86.git/commitdiff
clk: imx: Fix reparenting of UARTs not associated with stdout
authorAdam Ford <aford173@gmail.com>
Sat, 13 Mar 2021 12:28:17 +0000 (06:28 -0600)
committerAbel Vesa <abel.vesa@nxp.com>
Sun, 4 Apr 2021 19:39:04 +0000 (22:39 +0300)
Most if not all i.MX SoC's call a function which enables all UARTS.
This is a problem for users who need to re-parent the clock source,
because any attempt to change the parent results in an busy error
due to the fact that the clocks have been enabled already.

  clk: failed to reparent uart1 to sys_pll1_80m: -16

Instead of pre-initializing all UARTS, scan the device tree to see
which UART clocks are associated to stdout, and only enable those
UART clocks if it's needed early.  This will move initialization of
the remaining clocks until after the parenting of the clocks.

When the clocks are shutdown, this mechanism will also disable any
clocks that were pre-initialized.

Fixes: 9461f7b33d11c ("clk: fix CLK_SET_RATE_GATE with clock rate protection")
Suggested-by: Aisheng Dong <aisheng.dong@nxp.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
16 files changed:
drivers/clk/imx/clk-imx25.c
drivers/clk/imx/clk-imx27.c
drivers/clk/imx/clk-imx35.c
drivers/clk/imx/clk-imx5.c
drivers/clk/imx/clk-imx6q.c
drivers/clk/imx/clk-imx6sl.c
drivers/clk/imx/clk-imx6sll.c
drivers/clk/imx/clk-imx6sx.c
drivers/clk/imx/clk-imx7d.c
drivers/clk/imx/clk-imx7ulp.c
drivers/clk/imx/clk-imx8mm.c
drivers/clk/imx/clk-imx8mn.c
drivers/clk/imx/clk-imx8mp.c
drivers/clk/imx/clk-imx8mq.c
drivers/clk/imx/clk.c
drivers/clk/imx/clk.h

index a66cabfbf94f10807aca34aaa0aa317b0ff46f0c..66192fe0a898c1a568b7c44c02bf180c8dd1899a 100644 (file)
@@ -73,16 +73,6 @@ enum mx25_clks {
 
 static struct clk *clk[clk_max];
 
-static struct clk ** const uart_clks[] __initconst = {
-       &clk[uart_ipg_per],
-       &clk[uart1_ipg],
-       &clk[uart2_ipg],
-       &clk[uart3_ipg],
-       &clk[uart4_ipg],
-       &clk[uart5_ipg],
-       NULL
-};
-
 static int __init __mx25_clocks_init(void __iomem *ccm_base)
 {
        BUG_ON(!ccm_base);
@@ -228,7 +218,7 @@ static int __init __mx25_clocks_init(void __iomem *ccm_base)
         */
        clk_set_parent(clk[cko_sel], clk[ipg]);
 
-       imx_register_uart_clocks(uart_clks);
+       imx_register_uart_clocks(6);
 
        return 0;
 }
index 5585ded8b8c6fccaa80ac2d434f860554bd4ab24..56a5fc402b10c48487e79660b22c1acd541ce7c6 100644 (file)
@@ -49,17 +49,6 @@ static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
 static struct clk *clk[IMX27_CLK_MAX];
 static struct clk_onecell_data clk_data;
 
-static struct clk ** const uart_clks[] __initconst = {
-       &clk[IMX27_CLK_PER1_GATE],
-       &clk[IMX27_CLK_UART1_IPG_GATE],
-       &clk[IMX27_CLK_UART2_IPG_GATE],
-       &clk[IMX27_CLK_UART3_IPG_GATE],
-       &clk[IMX27_CLK_UART4_IPG_GATE],
-       &clk[IMX27_CLK_UART5_IPG_GATE],
-       &clk[IMX27_CLK_UART6_IPG_GATE],
-       NULL
-};
-
 static void __init _mx27_clocks_init(unsigned long fref)
 {
        BUG_ON(!ccm);
@@ -176,7 +165,7 @@ static void __init _mx27_clocks_init(unsigned long fref)
 
        clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]);
 
-       imx_register_uart_clocks(uart_clks);
+       imx_register_uart_clocks(7);
 
        imx_print_silicon_rev("i.MX27", mx27_revision());
 }
index c1df03665c09ae586cc5485605bfc380ecae3cef..0fe5ac210156607231a1390a5372c21cd3b89c0e 100644 (file)
@@ -82,14 +82,6 @@ enum mx35_clks {
 
 static struct clk *clk[clk_max];
 
-static struct clk ** const uart_clks[] __initconst = {
-       &clk[ipg],
-       &clk[uart1_gate],
-       &clk[uart2_gate],
-       &clk[uart3_gate],
-       NULL
-};
-
 static void __init _mx35_clocks_init(void)
 {
        void __iomem *base;
@@ -243,7 +235,7 @@ static void __init _mx35_clocks_init(void)
         */
        clk_prepare_enable(clk[scc_gate]);
 
-       imx_register_uart_clocks(uart_clks);
+       imx_register_uart_clocks(4);
 
        imx_print_silicon_rev("i.MX35", mx35_revision());
 }
index 01e079b810261738326539dc206489b00c1ede5e..e4493846454dd15fa9797ddc5f44acc546fd41b2 100644 (file)
@@ -128,30 +128,6 @@ static const char *ieee1588_sels[] = { "pll3_sw", "pll4_sw", "dummy" /* usbphy2_
 static struct clk *clk[IMX5_CLK_END];
 static struct clk_onecell_data clk_data;
 
-static struct clk ** const uart_clks_mx51[] __initconst = {
-       &clk[IMX5_CLK_UART1_IPG_GATE],
-       &clk[IMX5_CLK_UART1_PER_GATE],
-       &clk[IMX5_CLK_UART2_IPG_GATE],
-       &clk[IMX5_CLK_UART2_PER_GATE],
-       &clk[IMX5_CLK_UART3_IPG_GATE],
-       &clk[IMX5_CLK_UART3_PER_GATE],
-       NULL
-};
-
-static struct clk ** const uart_clks_mx50_mx53[] __initconst = {
-       &clk[IMX5_CLK_UART1_IPG_GATE],
-       &clk[IMX5_CLK_UART1_PER_GATE],
-       &clk[IMX5_CLK_UART2_IPG_GATE],
-       &clk[IMX5_CLK_UART2_PER_GATE],
-       &clk[IMX5_CLK_UART3_IPG_GATE],
-       &clk[IMX5_CLK_UART3_PER_GATE],
-       &clk[IMX5_CLK_UART4_IPG_GATE],
-       &clk[IMX5_CLK_UART4_PER_GATE],
-       &clk[IMX5_CLK_UART5_IPG_GATE],
-       &clk[IMX5_CLK_UART5_PER_GATE],
-       NULL
-};
-
 static void __init mx5_clocks_common_init(void __iomem *ccm_base)
 {
        clk[IMX5_CLK_DUMMY]             = imx_clk_fixed("dummy", 0);
@@ -382,7 +358,7 @@ static void __init mx50_clocks_init(struct device_node *np)
        r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
        clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
 
-       imx_register_uart_clocks(uart_clks_mx50_mx53);
+       imx_register_uart_clocks(5);
 }
 CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
 
@@ -488,7 +464,7 @@ static void __init mx51_clocks_init(struct device_node *np)
        val |= 1 << 23;
        writel(val, MXC_CCM_CLPCR);
 
-       imx_register_uart_clocks(uart_clks_mx51);
+       imx_register_uart_clocks(3);
 }
 CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
 
@@ -633,6 +609,6 @@ static void __init mx53_clocks_init(struct device_node *np)
        r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
        clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
 
-       imx_register_uart_clocks(uart_clks_mx50_mx53);
+       imx_register_uart_clocks(5);
 }
 CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
index 521d6136d22c5f36c63b8c0e50de5e65161153dc..496900de0b0bbf6eff60a28f7f37344a0f3a63d8 100644 (file)
@@ -140,13 +140,6 @@ static inline int clk_on_imx6dl(void)
        return of_machine_is_compatible("fsl,imx6dl");
 }
 
-static const int uart_clk_ids[] __initconst = {
-       IMX6QDL_CLK_UART_IPG,
-       IMX6QDL_CLK_UART_SERIAL,
-};
-
-static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata;
-
 static int ldb_di_sel_by_clock_id(int clock_id)
 {
        switch (clock_id) {
@@ -440,7 +433,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        struct device_node *np;
        void __iomem *anatop_base, *base;
        int ret;
-       int i;
 
        clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
                                          IMX6QDL_CLK_END), GFP_KERNEL);
@@ -982,12 +974,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
                               hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk);
        }
 
-       for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
-               int index = uart_clk_ids[i];
-
-               uart_clks[i] = &hws[index]->clk;
-       }
-
-       imx_register_uart_clocks(uart_clks);
+       imx_register_uart_clocks(1);
 }
 CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
index 29eab05c9068984cbd9c232cf4daa718604fbac6..277365970320299c5966039ad9aae0da448b51b8 100644 (file)
@@ -179,19 +179,11 @@ void imx6sl_set_wait_clk(bool enter)
                imx6sl_enable_pll_arm(false);
 }
 
-static const int uart_clk_ids[] __initconst = {
-       IMX6SL_CLK_UART,
-       IMX6SL_CLK_UART_SERIAL,
-};
-
-static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata;
-
 static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 {
        struct device_node *np;
        void __iomem *base;
        int ret;
-       int i;
 
        clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
                                          IMX6SL_CLK_END), GFP_KERNEL);
@@ -448,12 +440,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
        clk_set_parent(hws[IMX6SL_CLK_LCDIF_AXI_SEL]->clk,
                       hws[IMX6SL_CLK_PLL2_PFD2]->clk);
 
-       for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
-               int index = uart_clk_ids[i];
-
-               uart_clks[i] = &hws[index]->clk;
-       }
-
-       imx_register_uart_clocks(uart_clks);
+       imx_register_uart_clocks(2);
 }
 CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
index 8e8288bda4d0b6c9834ccb726008241ebd5ddaff..31d777f300395090613896d0f6947cfe9cf4694a 100644 (file)
@@ -76,26 +76,10 @@ static u32 share_count_ssi1;
 static u32 share_count_ssi2;
 static u32 share_count_ssi3;
 
-static const int uart_clk_ids[] __initconst = {
-       IMX6SLL_CLK_UART1_IPG,
-       IMX6SLL_CLK_UART1_SERIAL,
-       IMX6SLL_CLK_UART2_IPG,
-       IMX6SLL_CLK_UART2_SERIAL,
-       IMX6SLL_CLK_UART3_IPG,
-       IMX6SLL_CLK_UART3_SERIAL,
-       IMX6SLL_CLK_UART4_IPG,
-       IMX6SLL_CLK_UART4_SERIAL,
-       IMX6SLL_CLK_UART5_IPG,
-       IMX6SLL_CLK_UART5_SERIAL,
-};
-
-static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata;
-
 static void __init imx6sll_clocks_init(struct device_node *ccm_node)
 {
        struct device_node *np;
        void __iomem *base;
-       int i;
 
        clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
                                          IMX6SLL_CLK_END), GFP_KERNEL);
@@ -356,13 +340,7 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
 
        of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
 
-       for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
-               int index = uart_clk_ids[i];
-
-               uart_clks[i] = &hws[index]->clk;
-       }
-
-       imx_register_uart_clocks(uart_clks);
+       imx_register_uart_clocks(5);
 
        /* Lower the AHB clock rate before changing the clock source. */
        clk_set_rate(hws[IMX6SLL_CLK_AHB]->clk, 99000000);
index 20dcce526d072f98e5c0b29e509d75a57af00df5..fc1bd23d458340d85d4321e6f01df7cf92b646c9 100644 (file)
@@ -117,18 +117,10 @@ static u32 share_count_ssi3;
 static u32 share_count_sai1;
 static u32 share_count_sai2;
 
-static const int uart_clk_ids[] __initconst = {
-       IMX6SX_CLK_UART_IPG,
-       IMX6SX_CLK_UART_SERIAL,
-};
-
-static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata;
-
 static void __init imx6sx_clocks_init(struct device_node *ccm_node)
 {
        struct device_node *np;
        void __iomem *base;
-       int i;
 
        clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
                                          IMX6SX_CLK_CLK_END), GFP_KERNEL);
@@ -556,12 +548,6 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
        clk_set_parent(hws[IMX6SX_CLK_QSPI1_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk);
        clk_set_parent(hws[IMX6SX_CLK_QSPI2_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk);
 
-       for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
-               int index = uart_clk_ids[i];
-
-               uart_clks[i] = &hws[index]->clk;
-       }
-
-       imx_register_uart_clocks(uart_clks);
+       imx_register_uart_clocks(2);
 }
 CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
index 22d24a6a05e7040c9f8f52e88adcadd1dbb0ab3b..c4e0f1c07192f2d8ccd9c059940c104fe6205291 100644 (file)
@@ -377,23 +377,10 @@ static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_
 static struct clk_hw **hws;
 static struct clk_hw_onecell_data *clk_hw_data;
 
-static const int uart_clk_ids[] __initconst = {
-       IMX7D_UART1_ROOT_CLK,
-       IMX7D_UART2_ROOT_CLK,
-       IMX7D_UART3_ROOT_CLK,
-       IMX7D_UART4_ROOT_CLK,
-       IMX7D_UART5_ROOT_CLK,
-       IMX7D_UART6_ROOT_CLK,
-       IMX7D_UART7_ROOT_CLK,
-};
-
-static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata;
-
 static void __init imx7d_clocks_init(struct device_node *ccm_node)
 {
        struct device_node *np;
        void __iomem *base;
-       int i;
 
        clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
                                          IMX7D_CLK_END), GFP_KERNEL);
@@ -897,14 +884,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
        hws[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb1_main_clk", "osc", 20, 1);
        hws[IMX7D_USB_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb_main_clk", "osc", 20, 1);
 
-       for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
-               int index = uart_clk_ids[i];
-
-               uart_clks[i] = &hws[index]->clk;
-       }
-
-
-       imx_register_uart_clocks(uart_clks);
+       imx_register_uart_clocks(7);
 
 }
 CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init);
index 634c0b6636b0e47f40c350e4e4763a6c3e4f30d3..779e09105da7d19950a2583ad265491da2085948 100644 (file)
@@ -43,19 +43,6 @@ static const struct clk_div_table ulp_div_table[] = {
        { /* sentinel */ },
 };
 
-static const int pcc2_uart_clk_ids[] __initconst = {
-       IMX7ULP_CLK_LPUART4,
-       IMX7ULP_CLK_LPUART5,
-};
-
-static const int pcc3_uart_clk_ids[] __initconst = {
-       IMX7ULP_CLK_LPUART6,
-       IMX7ULP_CLK_LPUART7,
-};
-
-static struct clk **pcc2_uart_clks[ARRAY_SIZE(pcc2_uart_clk_ids) + 1] __initdata;
-static struct clk **pcc3_uart_clks[ARRAY_SIZE(pcc3_uart_clk_ids) + 1] __initdata;
-
 static void __init imx7ulp_clk_scg1_init(struct device_node *np)
 {
        struct clk_hw_onecell_data *clk_data;
@@ -150,7 +137,6 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
        struct clk_hw_onecell_data *clk_data;
        struct clk_hw **hws;
        void __iomem *base;
-       int i;
 
        clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC2_END),
                           GFP_KERNEL);
@@ -190,13 +176,7 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
 
        of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
 
-       for (i = 0; i < ARRAY_SIZE(pcc2_uart_clk_ids); i++) {
-               int index = pcc2_uart_clk_ids[i];
-
-               pcc2_uart_clks[i] = &hws[index]->clk;
-       }
-
-       imx_register_uart_clocks(pcc2_uart_clks);
+       imx_register_uart_clocks(2);
 }
 CLK_OF_DECLARE(imx7ulp_clk_pcc2, "fsl,imx7ulp-pcc2", imx7ulp_clk_pcc2_init);
 
@@ -205,7 +185,6 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
        struct clk_hw_onecell_data *clk_data;
        struct clk_hw **hws;
        void __iomem *base;
-       int i;
 
        clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC3_END),
                           GFP_KERNEL);
@@ -244,13 +223,7 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
 
        of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
 
-       for (i = 0; i < ARRAY_SIZE(pcc3_uart_clk_ids); i++) {
-               int index = pcc3_uart_clk_ids[i];
-
-               pcc3_uart_clks[i] = &hws[index]->clk;
-       }
-
-       imx_register_uart_clocks(pcc3_uart_clks);
+       imx_register_uart_clocks(7);
 }
 CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init);
 
index 6a01eec36dd04e0fcef628c3dac9f6e58b7875fe..f1919fafb1247a5a20d8c428277df1fc84d1b17f 100644 (file)
@@ -296,20 +296,12 @@ static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "
 static struct clk_hw_onecell_data *clk_hw_data;
 static struct clk_hw **hws;
 
-static const int uart_clk_ids[] = {
-       IMX8MM_CLK_UART1_ROOT,
-       IMX8MM_CLK_UART2_ROOT,
-       IMX8MM_CLK_UART3_ROOT,
-       IMX8MM_CLK_UART4_ROOT,
-};
-static struct clk **uart_hws[ARRAY_SIZE(uart_clk_ids) + 1];
-
 static int imx8mm_clocks_probe(struct platform_device *pdev)
 {
        struct device *dev = &pdev->dev;
        struct device_node *np = dev->of_node;
        void __iomem *base;
-       int ret, i;
+       int ret;
 
        clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
                                          IMX8MM_CLK_END), GFP_KERNEL);
@@ -634,13 +626,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
                goto unregister_hws;
        }
 
-       for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
-               int index = uart_clk_ids[i];
-
-               uart_hws[i] = &hws[index]->clk;
-       }
-
-       imx_register_uart_clocks(uart_hws);
+       imx_register_uart_clocks(4);
 
        return 0;
 
index 324c5fd0aa04fce971234f00cddfaa358a49f844..88f6630cd472f28f675fe133e9ec948c35988add 100644 (file)
@@ -289,20 +289,12 @@ static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "
 static struct clk_hw_onecell_data *clk_hw_data;
 static struct clk_hw **hws;
 
-static const int uart_clk_ids[] = {
-       IMX8MN_CLK_UART1_ROOT,
-       IMX8MN_CLK_UART2_ROOT,
-       IMX8MN_CLK_UART3_ROOT,
-       IMX8MN_CLK_UART4_ROOT,
-};
-static struct clk **uart_hws[ARRAY_SIZE(uart_clk_ids) + 1];
-
 static int imx8mn_clocks_probe(struct platform_device *pdev)
 {
        struct device *dev = &pdev->dev;
        struct device_node *np = dev->of_node;
        void __iomem *base;
-       int ret, i;
+       int ret;
 
        clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
                                          IMX8MN_CLK_END), GFP_KERNEL);
@@ -585,13 +577,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
                goto unregister_hws;
        }
 
-       for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
-               int index = uart_clk_ids[i];
-
-               uart_hws[i] = &hws[index]->clk;
-       }
-
-       imx_register_uart_clocks(uart_hws);
+       imx_register_uart_clocks(4);
 
        return 0;
 
index 2f4e1d674e1c12d96fa35277249e6d92df9958e8..3e6557e7d559b783bd5691205e047f358fa19c76 100644 (file)
@@ -414,20 +414,11 @@ static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_r
 static struct clk_hw **hws;
 static struct clk_hw_onecell_data *clk_hw_data;
 
-static const int uart_clk_ids[] = {
-       IMX8MP_CLK_UART1_ROOT,
-       IMX8MP_CLK_UART2_ROOT,
-       IMX8MP_CLK_UART3_ROOT,
-       IMX8MP_CLK_UART4_ROOT,
-};
-static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1];
-
 static int imx8mp_clocks_probe(struct platform_device *pdev)
 {
        struct device *dev = &pdev->dev;
        struct device_node *np;
        void __iomem *anatop_base, *ccm_base;
-       int i;
 
        np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop");
        anatop_base = of_iomap(np, 0);
@@ -737,13 +728,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 
        of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
 
-       for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
-               int index = uart_clk_ids[i];
-
-               uart_clks[i] = &hws[index]->clk;
-       }
-
-       imx_register_uart_clocks(uart_clks);
+       imx_register_uart_clocks(4);
 
        return 0;
 }
index 4dd4ae9d022baa315fb3c175c025efbcc6f5a6d2..3e1a10d3f55cc0a6bd1397f70d09aa31a8080b3b 100644 (file)
@@ -281,20 +281,12 @@ static const char * const pllout_monitor_sels[] = {"osc_25m", "osc_27m", "dummy"
 static struct clk_hw_onecell_data *clk_hw_data;
 static struct clk_hw **hws;
 
-static const int uart_clk_ids[] = {
-       IMX8MQ_CLK_UART1_ROOT,
-       IMX8MQ_CLK_UART2_ROOT,
-       IMX8MQ_CLK_UART3_ROOT,
-       IMX8MQ_CLK_UART4_ROOT,
-};
-static struct clk **uart_hws[ARRAY_SIZE(uart_clk_ids) + 1];
-
 static int imx8mq_clocks_probe(struct platform_device *pdev)
 {
        struct device *dev = &pdev->dev;
        struct device_node *np = dev->of_node;
        void __iomem *base;
-       int err, i;
+       int err;
 
        clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
                                          IMX8MQ_CLK_END), GFP_KERNEL);
@@ -629,13 +621,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
                goto unregister_hws;
        }
 
-       for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
-               int index = uart_clk_ids[i];
-
-               uart_hws[i] = &hws[index]->clk;
-       }
-
-       imx_register_uart_clocks(uart_hws);
+       imx_register_uart_clocks(4);
 
        return 0;
 
index 47882c51cb853753ace168bd95f1bd763765be63..7cc669934253a210e300b5e9d597091e9a6b1897 100644 (file)
@@ -147,8 +147,10 @@ void imx_cscmr1_fixup(u32 *val)
 }
 
 #ifndef MODULE
-static int imx_keep_uart_clocks;
-static struct clk ** const *imx_uart_clocks;
+
+static bool imx_keep_uart_clocks;
+static int imx_enabled_uart_clocks;
+static struct clk **imx_uart_clocks;
 
 static int __init imx_keep_uart_clocks_param(char *str)
 {
@@ -161,24 +163,45 @@ __setup_param("earlycon", imx_keep_uart_earlycon,
 __setup_param("earlyprintk", imx_keep_uart_earlyprintk,
              imx_keep_uart_clocks_param, 0);
 
-void imx_register_uart_clocks(struct clk ** const clks[])
+void imx_register_uart_clocks(unsigned int clk_count)
 {
+       imx_enabled_uart_clocks = 0;
+
+/* i.MX boards use device trees now.  For build tests without CONFIG_OF, do nothing */
+#ifdef CONFIG_OF
        if (imx_keep_uart_clocks) {
                int i;
 
-               imx_uart_clocks = clks;
-               for (i = 0; imx_uart_clocks[i]; i++)
-                       clk_prepare_enable(*imx_uart_clocks[i]);
+               imx_uart_clocks = kcalloc(clk_count, sizeof(struct clk *), GFP_KERNEL);
+
+               if (!of_stdout)
+                       return;
+
+               for (i = 0; i < clk_count; i++) {
+                       imx_uart_clocks[imx_enabled_uart_clocks] = of_clk_get(of_stdout, i);
+
+                       /* Stop if there are no more of_stdout references */
+                       if (IS_ERR(imx_uart_clocks[imx_enabled_uart_clocks]))
+                               return;
+
+                       /* Only enable the clock if it's not NULL */
+                       if (imx_uart_clocks[imx_enabled_uart_clocks])
+                               clk_prepare_enable(imx_uart_clocks[imx_enabled_uart_clocks++]);
+               }
        }
+#endif
 }
 
 static int __init imx_clk_disable_uart(void)
 {
-       if (imx_keep_uart_clocks && imx_uart_clocks) {
+       if (imx_keep_uart_clocks && imx_enabled_uart_clocks) {
                int i;
 
-               for (i = 0; imx_uart_clocks[i]; i++)
-                       clk_disable_unprepare(*imx_uart_clocks[i]);
+               for (i = 0; i < imx_enabled_uart_clocks; i++) {
+                       clk_disable_unprepare(imx_uart_clocks[i]);
+                       clk_put(imx_uart_clocks[i]);
+               }
+               kfree(imx_uart_clocks);
        }
 
        return 0;
index 4f04c8287286f2a3e3bf68f7e2709d28faf0e446..7571603bee23bd4a6a228ee6404ee760b547e9f6 100644 (file)
@@ -11,9 +11,9 @@ extern spinlock_t imx_ccm_lock;
 void imx_check_clocks(struct clk *clks[], unsigned int count);
 void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
 #ifndef MODULE
-void imx_register_uart_clocks(struct clk ** const clks[]);
+void imx_register_uart_clocks(unsigned int clk_count);
 #else
-static inline void imx_register_uart_clocks(struct clk ** const clks[])
+static inline void imx_register_uart_clocks(unsigned int clk_count)
 {
 }
 #endif