drm/nvc0-/gr: shift wrapping bug in nvc0_grctx_generate_r406800

We care about the upper 32 bits here so we have to use 1ULL instead of 1
to avoid a shift wrapping bug.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
index 64dca260912ff645c8dce1a338c56cb9ceadd1ef..fe67415c3e175ce17de2be2e8ba7e03570d97cf7 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
@@ -1039,7 +1039,7 @@ nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv)
                        } while (!tpcnr[gpc]);
                        tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
 
-                       tpc_set |= 1 << ((gpc * 8) + tpc);
+                       tpc_set |= 1ULL << ((gpc * 8) + tpc);
                }
 
                nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));