set _WORKAREASIZE 0x10000
}
+# Nonzero FLASHSIZE supresses QSPI flash size detection
+if { [info exists FLASHSIZE] } {
+ set _FLASHSIZE $FLASHSIZE
+} else {
+ # Detect QSPI flash size based on flash ID or SFDP
+ set _FLASHSIZE 0
+}
+
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
target create $_TARGETNAME_0 cortex_m -dap $_CHIPNAME.dap0 -coreid 0
# srst does not exist; use SYSRESETREQ to perform a soft reset
$_TARGETNAME_0 cortex_m reset_config sysresetreq
+
+ # After a rescue reset and fi BOOTSEL is halted connect the flash to enable
+ # reads from the XIP cached mapping area
+ $_TARGETNAME_0 configure -event reset-init { rp2xxx rom_api_call 0 CX }
}
# core 1
} else {
set _FLASH_TARGET $_TARGETNAME_0
}
-# Backup the work area. The flash probe runs an algorithm on the target CPU.
-# The flash is probed during gdb connect if gdb memory_map is enabled (by default).
-$_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup 1
+# QSPI flash size detection during gdb connect requires to back-up RAM
+set _WKA_BACKUP [expr { $_FLASHSIZE == 0 }]
+$_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup $_WKA_BACKUP
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME rp2xxx 0x10000000 0 0 0 $_FLASH_TARGET
+flash bank $_FLASHNAME rp2xxx 0x10000000 $_FLASHSIZE 0 0 $_FLASH_TARGET
if { $_BOTH_CORES } {
# Alias to ensure gdb connecting to core 1 gets the correct memory map