void pnv_ocxl_spa_release(void *platform_data);
 int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int pe_handle);
 
-int pnv_ocxl_alloc_xive_irq(u32 *irq, u64 *trigger_addr);
-void pnv_ocxl_free_xive_irq(u32 irq);
-
 #endif /* _ASM_PNV_OCXL_H */
 
 // Copyright 2017 IBM Corp.
 #include <asm/pnv-ocxl.h>
 #include <asm/opal.h>
-#include <asm/xive.h>
 #include <misc/ocxl-config.h>
 #include "pci.h"
 
        return rc;
 }
 EXPORT_SYMBOL_GPL(pnv_ocxl_spa_remove_pe_from_cache);
-
-int pnv_ocxl_alloc_xive_irq(u32 *irq, u64 *trigger_addr)
-{
-       __be64 flags, trigger_page;
-       s64 rc;
-       u32 hwirq;
-
-       hwirq = xive_native_alloc_irq();
-       if (!hwirq)
-               return -ENOENT;
-
-       rc = opal_xive_get_irq_info(hwirq, &flags, NULL, &trigger_page, NULL,
-                               NULL);
-       if (rc || !trigger_page) {
-               xive_native_free_irq(hwirq);
-               return -ENOENT;
-       }
-       *irq = hwirq;
-       *trigger_addr = be64_to_cpu(trigger_page);
-       return 0;
-
-}
-EXPORT_SYMBOL_GPL(pnv_ocxl_alloc_xive_irq);
-
-void pnv_ocxl_free_xive_irq(u32 irq)
-{
-       xive_native_free_irq(irq);
-}
-EXPORT_SYMBOL_GPL(pnv_ocxl_free_xive_irq);