drm/amd/display: Attempt to avoid empty TUs when endpoint is DPIA

[WHY]
Empty SST TUs are illegal to transmit over a USB4 DP tunnel.
Current policy is to configure stream encoder to pack 2 pixels per pclk
even when ODM combine is not in use, allowing seamless dynamic ODM
reconfiguration. However, in extreme edge cases where average pixel
count per TU is less than 2, this can lead to unexpected empty TU
generation during compliance testing. For example, VIC 1 with a 1xHBR3
link configuration will average 1.98 pix/TU.

[HOW]
Calculate average pixel count per TU, and block 2 pixels per clock if
endpoint is a DPIA tunnel and pixel clock is low enough that we will
never require 2:1 ODM combine.

Cc: stable@vger.kernel.org # 6.6+
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index 4f87316e1318bbf9406dd594f829401ea13c6838..0602921399cd182dd95c5c2339265e74151da93b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -1529,3 +1529,75 @@ void dcn35_set_long_vblank(struct pipe_ctx **pipe_ctx,
                }
        }
 }
+
+static bool should_avoid_empty_tu(struct pipe_ctx *pipe_ctx)
+{
+       /* Calculate average pixel count per TU, return false if under ~2.00 to
+        * avoid empty TUs. This is only required for DPIA tunneling as empty TUs
+        * are legal to generate for native DP links. Assume TU size 64 as there
+        * is currently no scenario where it's reprogrammed from HW default.
+        * MTPs have no such limitation, so this does not affect MST use cases.
+        */
+       unsigned int pix_clk_mhz;
+       unsigned int symclk_mhz;
+       unsigned int avg_pix_per_tu_x1000;
+       unsigned int tu_size_bytes = 64;
+       struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
+       struct dc_link_settings *link_settings = &pipe_ctx->link_config.dp_link_settings;
+       const struct dc *dc = pipe_ctx->stream->link->dc;
+
+       if (pipe_ctx->stream->link->ep_type != DISPLAY_ENDPOINT_USB4_DPIA)
+               return false;
+
+       // Not necessary for MST configurations
+       if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
+               return false;
+
+       pix_clk_mhz = timing->pix_clk_100hz / 10000;
+
+       // If this is true, can't block due to dynamic ODM
+       if (pix_clk_mhz > dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz)
+               return false;
+
+       switch (link_settings->link_rate) {
+       case LINK_RATE_LOW:
+               symclk_mhz = 162;
+               break;
+       case LINK_RATE_HIGH:
+               symclk_mhz = 270;
+               break;
+       case LINK_RATE_HIGH2:
+               symclk_mhz = 540;
+               break;
+       case LINK_RATE_HIGH3:
+               symclk_mhz = 810;
+               break;
+       default:
+               // We shouldn't be tunneling any other rates, something is wrong
+               ASSERT(0);
+               return false;
+       }
+
+       avg_pix_per_tu_x1000 = (1000 * pix_clk_mhz * tu_size_bytes)
+               / (symclk_mhz * link_settings->lane_count);
+
+       // Add small empirically-decided margin to account for potential jitter
+       return (avg_pix_per_tu_x1000 < 2020);
+}
+
+bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)
+{
+       struct dc *dc = pipe_ctx->stream->ctx->dc;
+
+       if (!is_h_timing_divisible_by_2(pipe_ctx->stream))
+               return false;
+
+       if (should_avoid_empty_tu(pipe_ctx))
+               return false;
+
+       if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) &&
+               dc->debug.enable_dp_dig_pixel_rate_div_policy)
+               return true;
+
+       return false;
+}

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
index bc05beba5f2ce69074525be94c00c38a887b9c19..e27b3609020ffd29f7461216e236446f90fab847 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
@@ -97,4 +97,6 @@ void dcn35_set_static_screen_control(struct pipe_ctx **pipe_ctx,
 void dcn35_set_long_vblank(struct pipe_ctx **pipe_ctx,
                int num_pipes, uint32_t v_total_min, uint32_t v_total_max);
 
+bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);
+
 #endif /* __DC_HWSS_DCN35_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
index 30e6a639883910ac4e5360104eb4b404cb0d4d0c..428912f371291b11d0266b7c25cc366b5f82f78d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
@@ -161,7 +161,7 @@ static const struct hwseq_private_funcs dcn35_private_funcs = {
        .setup_hpo_hw_control = dcn35_setup_hpo_hw_control,
        .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,
        .resync_fifo_dccg_dio = dcn314_resync_fifo_dccg_dio,
-       .is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy,
+       .is_dp_dig_pixel_rate_div_policy = dcn35_is_dp_dig_pixel_rate_div_policy,
        .dsc_pg_control = dcn35_dsc_pg_control,
        .dsc_pg_status = dcn32_dsc_pg_status,
        .enable_plane = dcn35_enable_plane,