struct intel_crtc_state *old_crtc_state, *new_crtc_state;
        unsigned int updated = 0;
        bool progress;
-       enum pipe pipe;
        int i;
        u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
        u8 required_slices = state->wm_results.ddb.enabled_slices;
                progress = false;
 
                for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+                       enum pipe pipe = crtc->pipe;
                        bool vbl_wait = false;
-                       unsigned int cmask = drm_crtc_mask(&crtc->base);
-
-                       pipe = crtc->pipe;
 
-                       if (updated & cmask || !new_crtc_state->base.active)
+                       if (updated & BIT(crtc->pipe) || !new_crtc_state->base.active)
                                continue;
 
                        if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
                                                        INTEL_NUM_PIPES(dev_priv), i))
                                continue;
 
-                       updated |= cmask;
+                       updated |= BIT(pipe);
                        entries[i] = new_crtc_state->wm.skl.ddb;
 
                        /*
 
                if (!skl_pipe_wm_equals(crtc,
                                        &old_crtc_state->wm.skl.optimal,
                                        &new_crtc_state->wm.skl.optimal))
-                       results->dirty_pipes |= drm_crtc_mask(&crtc->base);
+                       results->dirty_pipes |= BIT(crtc->pipe);
        }
 
        ret = skl_compute_ddb(state);
        struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
        enum pipe pipe = crtc->pipe;
 
-       if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
+       if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0)
                return;
 
        I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
 static void skl_initial_wm(struct intel_atomic_state *state,
                           struct intel_crtc_state *crtc_state)
 {
-       struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
-       struct drm_device *dev = intel_crtc->base.dev;
-       struct drm_i915_private *dev_priv = to_i915(dev);
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        struct skl_ddb_values *results = &state->wm_results;
 
-       if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
+       if ((results->dirty_pipes & BIT(crtc->pipe)) == 0)
                return;
 
        mutex_lock(&dev_priv->wm.wm_mutex);
                skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
 
                if (crtc->active)
-                       hw->dirty_pipes |= drm_crtc_mask(&crtc->base);
+                       hw->dirty_pipes |= BIT(crtc->pipe);
        }
 
        if (dev_priv->active_pipes) {