scsi: ufs: exynos: Set ACG to be controlled by UFS_ACG_DISABLE

HCI_IOP_ACG_DISABLE is an undocumented register in the TRM but the
downstream driver sets this register so we follow suit here.

The register is already 0 presumed to be set by the bootloader as the
comment downstream implies the reset state is 1. So whilst this is a nop
currently, it should protect us in case the bootloader behaviour ever
changes.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20241031150033.3440894-12-peter.griffin@linaro.org
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index 78307440107f0ec025ef786221c8c8bf2db2e731..5078210b2a5ce8d7245062b15449124ca71707f7 100644 (file)
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -76,6 +76,10 @@
 #define CLK_CTRL_EN_MASK       (REFCLK_CTRL_EN |\
                                 UNIPRO_PCLK_CTRL_EN |\
                                 UNIPRO_MCLK_CTRL_EN)
+
+#define HCI_IOP_ACG_DISABLE    0x100
+#define HCI_IOP_ACG_DISABLE_EN BIT(0)
+
 /* Device fatal error */
 #define DFES_ERR_EN            BIT(31)
 #define DFES_DEF_L2_ERRS       (UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF |\
@@ -215,10 +219,15 @@ static int exynos_ufs_shareability(struct exynos_ufs *ufs)
 static int gs101_ufs_drv_init(struct exynos_ufs *ufs)
 {
        struct ufs_hba *hba = ufs->hba;
+       u32 reg;
 
        /* Enable WriteBooster */
        hba->caps |= UFSHCD_CAP_WB_EN;
 
+       /* set ACG to be controlled by UFS_ACG_DISABLE */
+       reg = hci_readl(ufs, HCI_IOP_ACG_DISABLE);
+       hci_writel(ufs, reg & (~HCI_IOP_ACG_DISABLE_EN), HCI_IOP_ACG_DISABLE);
+
        return exynos_ufs_shareability(ufs);
 }