clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in comments

The multipliers for PLL2 and PLL4 as listed in the comments for
the cpg_pll_configs[] array are incorrect.  Fix them.

Note that the actual values in the tables were correct.

Fixes: f077cab34df3010d ("clk: renesas: cpg-mssr: Add support for R-Car V4M")
Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/07126b55807c1596422c9547e72f0a032487da1e.1718177076.git.geert+renesas@glider.be

diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
index 5ca1b14a6d608b081ea5ef4917fdedbad5870c55..1dda8ea4938d1f4f5d309087c96dad761a571012 100644 (file)
--- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
@@ -242,10 +242,10 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
  *   MD         EXTAL          PLL1    PLL2    PLL3    PLL4    PLL5    PLL6    OSC
  * 14 13 (MHz)
  * ------------------------------------------------------------------------
- * 0  0         16.66 / 1      x192    x204    x192    x144    x192    x168    /16
- * 0  1         20    / 1      x160    x170    x160    x120    x160    x140    /19
+ * 0  0         16.66 / 1      x192    x240    x192    x240    x192    x168    /16
+ * 0  1         20    / 1      x160    x200    x160    x200    x160    x140    /19
  * 1  0         Prohibited setting
- * 1  1         33.33 / 2      x192    x204    x192    x144    x192    x168    /32
+ * 1  1         33.33 / 2      x192    x240    x192    x240    x192    x168    /32
  */
 #define CPG_PLL_CONFIG_INDEX(md)       ((((md) & BIT(14)) >> 13) | \
                                         (((md) & BIT(13)) >> 13))