clk: qcom: apss-ipq-pll: move Huayra register map to 'clk_alpha_pll_regs'

Move the locally defined Huayra register map to 'clk_alpha_pll_regs'
in order to allow using that by other drivers, like the clk-cbf-8996.

No functional changes.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://lore.kernel.org/r/20240328-apss-ipq-pll-cleanup-v4-2-eddbf617f0c8@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
index ed3e6405f99cbb5be079f8c61dda469ca0bb3fd1..8cf17374a2e2a380bcfbfdb5e219fe2f8490b2ca 100644 (file)
--- a/drivers/clk/qcom/apss-ipq-pll.c
+++ b/drivers/clk/qcom/apss-ipq-pll.c
@@ -8,27 +8,9 @@
 
 #include "clk-alpha-pll.h"
 
-/*
- * Even though APSS PLL type is of existing one (like Huayra), its offsets
- * are different from the one mentioned in the clk-alpha-pll.c, since the
- * PLL is specific to APSS, so lets the define the same.
- */
-static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = {
-       [CLK_ALPHA_PLL_TYPE_HUAYRA] =  {
-               [PLL_OFF_L_VAL] = 0x08,
-               [PLL_OFF_ALPHA_VAL] = 0x10,
-               [PLL_OFF_USER_CTL] = 0x18,
-               [PLL_OFF_CONFIG_CTL] = 0x20,
-               [PLL_OFF_CONFIG_CTL_U] = 0x24,
-               [PLL_OFF_STATUS] = 0x28,
-               [PLL_OFF_TEST_CTL] = 0x30,
-               [PLL_OFF_TEST_CTL_U] = 0x34,
-       },
-};
-
 static struct clk_alpha_pll ipq_pll_huayra = {
        .offset = 0x0,
-       .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_HUAYRA],
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_APSS],
        .flags = SUPPORTS_DYNAMIC_UPDATE,
        .clkr = {
                .enable_reg = 0x0,

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 7f0ed5bd51e3defddbf1b36d237fab2df65bb16d..236794cb3e50109f3cfbcc8d20de6431e5329ccb 100644 (file)
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -83,6 +83,16 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
                [PLL_OFF_TEST_CTL_U] = 0x20,
                [PLL_OFF_STATUS] = 0x24,
        },
+       [CLK_ALPHA_PLL_TYPE_HUAYRA_APSS] =  {
+               [PLL_OFF_L_VAL] = 0x08,
+               [PLL_OFF_ALPHA_VAL] = 0x10,
+               [PLL_OFF_USER_CTL] = 0x18,
+               [PLL_OFF_CONFIG_CTL] = 0x20,
+               [PLL_OFF_CONFIG_CTL_U] = 0x24,
+               [PLL_OFF_STATUS] = 0x28,
+               [PLL_OFF_TEST_CTL] = 0x30,
+               [PLL_OFF_TEST_CTL_U] = 0x34,
+       },
        [CLK_ALPHA_PLL_TYPE_BRAMMO] =  {
                [PLL_OFF_L_VAL] = 0x04,
                [PLL_OFF_ALPHA_VAL] = 0x08,

diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 1bb2d031dc9fa87b16f4e60807f1a092c168f2cc..c7055b6c42f1d522346ff2339613c47091cddf59 100644 (file)
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -15,6 +15,7 @@
 enum {
        CLK_ALPHA_PLL_TYPE_DEFAULT,
        CLK_ALPHA_PLL_TYPE_HUAYRA,
+       CLK_ALPHA_PLL_TYPE_HUAYRA_APSS,
        CLK_ALPHA_PLL_TYPE_BRAMMO,
        CLK_ALPHA_PLL_TYPE_FABIA,
        CLK_ALPHA_PLL_TYPE_TRION,