pinctrl: renesas: rzg2l: Adapt function number for RZ/G3S

On RZ/G3S PFC register allow setting 8 functions for individual ports
(function1 to function8). For function1 the register need to be
configured with 0, for function8 the register need to be configured with
7.  We cannot use zero based addressing when requesting functions from
different code places as the documentation
(RZG3S_pinfunction_List_r1.0.xlsx) states explicitly that function0 is
GPIO.

Add a new member to struct rzg2l_hwcfg that will keep the offset that
needs to be substracted before applying a value to a PFC register.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-17-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index a5d0a5c3264442d93d295b68836a1b12d5234ad4..805280dfd697b0ccdcc05993a3e75e909517bf4c 100644 (file)
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -136,9 +136,11 @@ struct rzg2l_register_offsets {
 /**
  * struct rzg2l_hwcfg - hardware configuration data structure
  * @regs: hardware specific register offsets
+ * @func_base: base number for port function (see register PFC)
  */
 struct rzg2l_hwcfg {
        const struct rzg2l_register_offsets regs;
+       u8 func_base;
 };
 
 struct rzg2l_dedicated_configs {
@@ -221,6 +223,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,
                                 unsigned int group_selector)
 {
        struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+       const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
        struct function_desc *func;
        unsigned int i, *psel_val;
        struct group_desc *group;
@@ -242,9 +245,9 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,
                u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]);
 
                dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n",
-                       RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i]);
+                       RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base);
 
-               rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i]);
+               rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base);
        }
 
        return 0;