clk: renesas: rzg2l-cpg: Refactor to use priv for clks and base in clock register...

Simplify the `rzg2l-cpg` driver by removing explicit passing of `clks` and
`base` parameters in various clock registration functions. These values
are now accessed directly from the `priv` structure.

While at it, drop masking of parent clocks with 0xffff as nothing is ever
stored in the high bits.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240715103555.507767-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index f330805e7d8a8fae20064da2078f28974fbe3363..88bf39e8c79c837869d4b2d07d53e7b7bc89cef0 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -339,8 +339,7 @@ static const struct clk_ops rzg3s_div_clk_ops = {
 };
 
 static struct clk * __init
-rzg3s_cpg_div_clk_register(const struct cpg_core_clk *core, struct clk **clks,
-                          void __iomem *base, struct rzg2l_cpg_priv *priv)
+rzg3s_cpg_div_clk_register(const struct cpg_core_clk *core, struct rzg2l_cpg_priv *priv)
 {
        struct div_hw_data *div_hw_data;
        struct clk_init_data init = {};
@@ -351,7 +350,7 @@ rzg3s_cpg_div_clk_register(const struct cpg_core_clk *core, struct clk **clks,
        u32 max = 0;
        int ret;
 
-       parent = clks[core->parent & 0xffff];
+       parent = priv->clks[core->parent];
        if (IS_ERR(parent))
                return ERR_CAST(parent);
 
@@ -400,16 +399,15 @@ rzg3s_cpg_div_clk_register(const struct cpg_core_clk *core, struct clk **clks,
 
 static struct clk * __init
 rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core,
-                          struct clk **clks,
-                          void __iomem *base,
                           struct rzg2l_cpg_priv *priv)
 {
+       void __iomem *base = priv->base;
        struct device *dev = priv->dev;
        const struct clk *parent;
        const char *parent_name;
        struct clk_hw *clk_hw;
 
-       parent = clks[core->parent & 0xffff];
+       parent = priv->clks[core->parent];
        if (IS_ERR(parent))
                return ERR_CAST(parent);
 
@@ -440,7 +438,6 @@ rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core,
 
 static struct clk * __init
 rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core,
-                          void __iomem *base,
                           struct rzg2l_cpg_priv *priv)
 {
        const struct clk_hw *clk_hw;
@@ -448,7 +445,7 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core,
        clk_hw = devm_clk_hw_register_mux(priv->dev, core->name,
                                          core->parent_names, core->num_parents,
                                          core->flag,
-                                         base + GET_REG_OFFSET(core->conf),
+                                         priv->base + GET_REG_OFFSET(core->conf),
                                          GET_SHIFT(core->conf),
                                          GET_WIDTH(core->conf),
                                          core->mux_flags, &priv->rmw_lock);
@@ -508,7 +505,6 @@ static const struct clk_ops rzg2l_cpg_sd_clk_mux_ops = {
 
 static struct clk * __init
 rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core,
-                             void __iomem *base,
                              struct rzg2l_cpg_priv *priv)
 {
        struct sd_mux_hw_data *sd_mux_hw_data;
@@ -652,7 +648,6 @@ static const struct clk_ops rzg2l_cpg_dsi_div_ops = {
 
 static struct clk * __init
 rzg2l_cpg_dsi_div_clk_register(const struct cpg_core_clk *core,
-                              struct clk **clks,
                               struct rzg2l_cpg_priv *priv)
 {
        struct dsi_div_hw_data *clk_hw_data;
@@ -662,7 +657,7 @@ rzg2l_cpg_dsi_div_clk_register(const struct cpg_core_clk *core,
        struct clk_hw *clk_hw;
        int ret;
 
-       parent = clks[core->parent & 0xffff];
+       parent = priv->clks[core->parent];
        if (IS_ERR(parent))
                return ERR_CAST(parent);
 
@@ -900,7 +895,6 @@ static const struct clk_ops rzg2l_cpg_sipll5_ops = {
 
 static struct clk * __init
 rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
-                         struct clk **clks,
                          struct rzg2l_cpg_priv *priv)
 {
        const struct clk *parent;
@@ -910,7 +904,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
        struct clk_hw *clk_hw;
        int ret;
 
-       parent = clks[core->parent & 0xffff];
+       parent = priv->clks[core->parent];
        if (IS_ERR(parent))
                return ERR_CAST(parent);
 
@@ -1013,8 +1007,6 @@ static const struct clk_ops rzg3s_cpg_pll_ops = {
 
 static struct clk * __init
 rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
-                          struct clk **clks,
-                          void __iomem *base,
                           struct rzg2l_cpg_priv *priv,
                           const struct clk_ops *ops)
 {
@@ -1025,7 +1017,7 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
        struct pll_clk *pll_clk;
        int ret;
 
-       parent = clks[core->parent & 0xffff];
+       parent = priv->clks[core->parent];
        if (IS_ERR(parent))
                return ERR_CAST(parent);
 
@@ -1042,7 +1034,7 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
 
        pll_clk->hw.init = &init;
        pll_clk->conf = core->conf;
-       pll_clk->base = base;
+       pll_clk->base = priv->base;
        pll_clk->priv = priv;
        pll_clk->type = core->type;
 
@@ -1139,34 +1131,31 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
                        clk = clk_hw->clk;
                break;
        case CLK_TYPE_SAM_PLL:
-               clk = rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv,
-                                                &rzg2l_cpg_pll_ops);
+               clk = rzg2l_cpg_pll_clk_register(core, priv, &rzg2l_cpg_pll_ops);
                break;
        case CLK_TYPE_G3S_PLL:
-               clk = rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv,
-                                                &rzg3s_cpg_pll_ops);
+               clk = rzg2l_cpg_pll_clk_register(core, priv, &rzg3s_cpg_pll_ops);
                break;
        case CLK_TYPE_SIPLL5:
-               clk = rzg2l_cpg_sipll5_register(core, priv->clks, priv);
+               clk = rzg2l_cpg_sipll5_register(core, priv);
                break;
        case CLK_TYPE_DIV:
-               clk = rzg2l_cpg_div_clk_register(core, priv->clks,
-                                                priv->base, priv);
+               clk = rzg2l_cpg_div_clk_register(core, priv);
                break;
        case CLK_TYPE_G3S_DIV:
-               clk = rzg3s_cpg_div_clk_register(core, priv->clks, priv->base, priv);
+               clk = rzg3s_cpg_div_clk_register(core, priv);
                break;
        case CLK_TYPE_MUX:
-               clk = rzg2l_cpg_mux_clk_register(core, priv->base, priv);
+               clk = rzg2l_cpg_mux_clk_register(core, priv);
                break;
        case CLK_TYPE_SD_MUX:
-               clk = rzg2l_cpg_sd_mux_clk_register(core, priv->base, priv);
+               clk = rzg2l_cpg_sd_mux_clk_register(core, priv);
                break;
        case CLK_TYPE_PLL5_4_MUX:
                clk = rzg2l_cpg_pll5_4_mux_clk_register(core, priv);
                break;
        case CLK_TYPE_DSI_DIV:
-               clk = rzg2l_cpg_dsi_div_clk_register(core, priv->clks, priv);
+               clk = rzg2l_cpg_dsi_div_clk_register(core, priv);
                break;
        default:
                goto fail;