]> www.infradead.org Git - linux-platform-drivers-x86.git/commitdiff
mmc: sunxi: add support for A100 mmc controller
authorYangtao Li <frank@allwinnertech.com>
Fri, 11 Dec 2020 01:19:22 +0000 (01:19 +0000)
committerUlf Hansson <ulf.hansson@linaro.org>
Mon, 1 Feb 2021 10:54:42 +0000 (11:54 +0100)
This patch adds support for A100 MMC controller, which use word address
for internal dma.

Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20201211011934.6171-10-andre.przywara@arm.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
drivers/mmc/host/sunxi-mmc.c

index 6310693f2ac06d2145d8e951afb13923eb6fa6c8..e46bb4e404a89bec2b26226c2b94a5018c7dfe1e 100644 (file)
@@ -245,6 +245,7 @@ struct sunxi_idma_des {
 
 struct sunxi_mmc_cfg {
        u32 idma_des_size_bits;
+       u32 idma_des_shift;
        const struct sunxi_mmc_clk_delay *clk_delays;
 
        /* does the IP block support autocalibration? */
@@ -344,7 +345,7 @@ static int sunxi_mmc_init_host(struct sunxi_mmc_host *host)
        /* Enable CEATA support */
        mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
        /* Set DMA descriptor list base address */
-       mmc_writel(host, REG_DLBA, host->sg_dma);
+       mmc_writel(host, REG_DLBA, host->sg_dma >> host->cfg->idma_des_shift);
 
        rval = mmc_readl(host, REG_GCTRL);
        rval |= SDXC_INTERRUPT_ENABLE_BIT;
@@ -374,8 +375,10 @@ static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
 
                next_desc += sizeof(struct sunxi_idma_des);
                pdes[i].buf_addr_ptr1 =
-                       cpu_to_le32(sg_dma_address(&data->sg[i]));
-               pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc);
+                       cpu_to_le32(sg_dma_address(&data->sg[i]) >>
+                                   host->cfg->idma_des_shift);
+               pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc >>
+                                                   host->cfg->idma_des_shift);
        }
 
        pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);
@@ -1179,6 +1182,23 @@ static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
        .needs_new_timings = true,
 };
 
+static const struct sunxi_mmc_cfg sun50i_a100_cfg = {
+       .idma_des_size_bits = 16,
+       .idma_des_shift = 2,
+       .clk_delays = NULL,
+       .can_calibrate = true,
+       .mask_data0 = true,
+       .needs_new_timings = true,
+};
+
+static const struct sunxi_mmc_cfg sun50i_a100_emmc_cfg = {
+       .idma_des_size_bits = 13,
+       .idma_des_shift = 2,
+       .clk_delays = NULL,
+       .can_calibrate = true,
+       .needs_new_timings = true,
+};
+
 static const struct of_device_id sunxi_mmc_of_match[] = {
        { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
        { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
@@ -1187,6 +1207,8 @@ static const struct of_device_id sunxi_mmc_of_match[] = {
        { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
        { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
        { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
+       { .compatible = "allwinner,sun50i-a100-mmc", .data = &sun50i_a100_cfg },
+       { .compatible = "allwinner,sun50i-a100-emmc", .data = &sun50i_a100_emmc_cfg },
        { /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);