static const struct aspeed_gate_data aspeed_g6_gates[] = {
        /*                                  clk rst  name               parent   flags */
        [ASPEED_CLK_GATE_MCLK]          = {  0, -1, "mclk-gate",        "mpll",  CLK_IS_CRITICAL }, /* SDRAM */
-       [ASPEED_CLK_GATE_ECLK]          = {  1, -1, "eclk-gate",        "eclk",  0 },   /* Video Engine */
+       [ASPEED_CLK_GATE_ECLK]          = {  1,  6, "eclk-gate",        "eclk",  0 },   /* Video Engine */
        [ASPEED_CLK_GATE_GCLK]          = {  2,  7, "gclk-gate",        NULL,    0 },   /* 2D engine */
        /* vclk parent - dclk/d1clk/hclk/mclk */
-       [ASPEED_CLK_GATE_VCLK]          = {  3,  6, "vclk-gate",        NULL,    0 },   /* Video Capture */
+       [ASPEED_CLK_GATE_VCLK]          = {  3, -1, "vclk-gate",        NULL,    0 },   /* Video Capture */
        [ASPEED_CLK_GATE_BCLK]          = {  4,  8, "bclk-gate",        "bclk",  0 }, /* PCIe/PCI */
        /* From dpll */
        [ASPEED_CLK_GATE_DCLK]          = {  5, -1, "dclk-gate",        NULL,    CLK_IS_CRITICAL }, /* DAC */
 
        aspeed_video_write(video, VE_INTERRUPT_STATUS, 0xffffffff);
 
        /* Turn off the relevant clocks */
-       clk_disable(video->vclk);
        clk_disable(video->eclk);
+       clk_disable(video->vclk);
 
        clear_bit(VIDEO_CLOCKS_ON, &video->flags);
 }
                return;
 
        /* Turn on the relevant clocks */
-       clk_enable(video->eclk);
        clk_enable(video->vclk);
+       clk_enable(video->eclk);
 
        set_bit(VIDEO_CLOCKS_ON, &video->flags);
 }
                return rc;
 
        rc = aspeed_video_setup_video(video);
-       if (rc)
+       if (rc) {
+               clk_unprepare(video->vclk);
+               clk_unprepare(video->eclk);
                return rc;
+       }
 
        return 0;
 }