struct rcar_canfd_hw_info {
        enum rcanfd_chip_id chip_id;
+       u8 max_channels;
 };
 
 /* Channel priv data */
        struct reset_control *rstc1;
        struct reset_control *rstc2;
        const struct rcar_canfd_hw_info *info;
-       u32 max_channels;
 };
 
 /* CAN FD mode nominal rate constants */
 
 static const struct rcar_canfd_hw_info rcar_gen3_hw_info = {
        .chip_id = RENESAS_RCAR_GEN3,
+       .max_channels = 2,
 };
 
 static const struct rcar_canfd_hw_info rzg2l_hw_info = {
        .chip_id = RENESAS_RZG2L,
+       .max_channels = 2,
 };
 
 static const struct rcar_canfd_hw_info r8a779a0_hw_info = {
        .chip_id = RENESAS_R8A779A0,
+       .max_channels = 8,
 };
 
 /* Helper functions */
        rcar_canfd_set_mode(gpriv);
 
        /* Transition all Channels to reset mode */
-       for_each_set_bit(ch, &gpriv->channels_mask, gpriv->max_channels) {
+       for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
                rcar_canfd_clear_bit(gpriv->base,
                                     RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
 
        rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg);
 
        /* Channel configuration settings */
-       for_each_set_bit(ch, &gpriv->channels_mask, gpriv->max_channels) {
+       for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
                rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch),
                                   RCANFD_CCTR_ERRD);
                rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
        struct rcar_canfd_global *gpriv = dev_id;
        u32 ch;
 
-       for_each_set_bit(ch, &gpriv->channels_mask, gpriv->max_channels)
+       for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels)
                rcar_canfd_handle_global_err(gpriv, ch);
 
        return IRQ_HANDLED;
        struct rcar_canfd_global *gpriv = dev_id;
        u32 ch;
 
-       for_each_set_bit(ch, &gpriv->channels_mask, gpriv->max_channels)
+       for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels)
                rcar_canfd_handle_global_receive(gpriv, ch);
 
        return IRQ_HANDLED;
        /* Global error interrupts still indicate a condition specific
         * to a channel. RxFIFO interrupt is a global interrupt.
         */
-       for_each_set_bit(ch, &gpriv->channels_mask, gpriv->max_channels) {
+       for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
                rcar_canfd_handle_global_err(gpriv, ch);
                rcar_canfd_handle_global_receive(gpriv, ch);
        }
        u32 ch;
 
        /* Common FIFO is a per channel resource */
-       for_each_set_bit(ch, &gpriv->channels_mask, gpriv->max_channels) {
+       for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
                rcar_canfd_handle_channel_err(gpriv, ch);
                rcar_canfd_handle_channel_tx(gpriv, ch);
        }
        int err, ch_irq, g_irq;
        int g_err_irq, g_recc_irq;
        bool fdmode = true;                     /* CAN FD only mode - default */
-       int max_channels;
        char name[9] = "channelX";
        int i;
 
        info = of_device_get_match_data(&pdev->dev);
-       max_channels = info->chip_id == RENESAS_R8A779A0 ? 8 : 2;
 
        if (of_property_read_bool(pdev->dev.of_node, "renesas,no-can-fd"))
                fdmode = false;                 /* Classical CAN only mode */
 
-       for (i = 0; i < max_channels; ++i) {
+       for (i = 0; i < info->max_channels; ++i) {
                name[7] = '0' + i;
                of_child = of_get_child_by_name(pdev->dev.of_node, name);
                if (of_child && of_device_is_available(of_child))
        gpriv->channels_mask = channels_mask;
        gpriv->fdmode = fdmode;
        gpriv->info = info;
-       gpriv->max_channels = max_channels;
 
        gpriv->rstc1 = devm_reset_control_get_optional_exclusive(&pdev->dev,
                                                                 "rstp_n");
        rcar_canfd_configure_controller(gpriv);
 
        /* Configure per channel attributes */
-       for_each_set_bit(ch, &gpriv->channels_mask, max_channels) {
+       for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels) {
                /* Configure Channel's Rx fifo */
                rcar_canfd_configure_rx(gpriv, ch);
 
                goto fail_mode;
        }
 
-       for_each_set_bit(ch, &gpriv->channels_mask, max_channels) {
+       for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels) {
                err = rcar_canfd_channel_probe(gpriv, ch, fcan_freq);
                if (err)
                        goto fail_channel;
        return 0;
 
 fail_channel:
-       for_each_set_bit(ch, &gpriv->channels_mask, max_channels)
+       for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels)
                rcar_canfd_channel_remove(gpriv, ch);
 fail_mode:
        rcar_canfd_disable_global_interrupts(gpriv);
        rcar_canfd_reset_controller(gpriv);
        rcar_canfd_disable_global_interrupts(gpriv);
 
-       for_each_set_bit(ch, &gpriv->channels_mask, gpriv->max_channels) {
+       for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
                rcar_canfd_disable_channel_interrupts(gpriv->ch[ch]);
                rcar_canfd_channel_remove(gpriv, ch);
        }