+======================================================================
+Recent changes
+======================================================================
+
+* Added support for ARM9 CPUs (Gary Jennejohn <gj@denx.de>)
+
======================================================================
Modifications for 1.0.2:
======================================================================
--- /dev/null
+#########################################################################
+# #
+# Regular Maintainers for PPCBoot board support: #
+# #
+# For any board without permanent maintainer, please contact #
+# Marius Gröger <mag@sysgo.de> #
+# and Cc: the <armboot-users@lists.sourceforge.net> mailing list. #
+# #
+#########################################################################
+# Maintainer Name, Email Address #
+# Board CPU #
+#########################################################################
+
+Marius Gröger <mag@sysgo.de>
+
+ impa7 ARM720T (EP7211)
+ ep7312 ARM720T (EP7312)
+
+Alex Züpke <azu@sysgo.de>
+
+ lart SA1100
+ dnp1110 SA1110
+
+Rolf Offermanns <rof@sysgo.de>
+
+ shannon SA1100
+
+Gary Jennejohn <gj@denx.de>
+
+ samsung ARM920T
+
+#########################################################################
+# End of MAINTAINERS list #
+#########################################################################
LIST_ARM7="impa7 ep7312"
+#########################################################################
+## ARM9 Systems
+#########################################################################
+
+LIST_ARM9="samsung"
-LIST_all="${LIST_SA} ${LIST_ARM7}"
+LIST_all="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9}"
[ $# = 0 ] && set $LIST_all
#
-# (C) Copyright 2000
+# (C) Copyright 2000, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2002
-e s/arm.*/arm/ \
-e s/sa110/arm/)
+ifndef CROSS_COMPILE
ifeq ($(HOSTARCH),arm)
CROSS_COMPILE =
else
CROSS_COMPILE = arm-linux-
endif
+endif
export CROSS_COMPILE HOSTARCH
echo "CPU = sa1100" >>config.mk ; \
echo "#include <configs/config_$(@:_config=).h>" >config.h
+#########################################################################
+## ARM920T Systems
+#########################################################################
+
+samsung_config : unconfig
+ @echo "Configuring for $(@:_config=) Board..." ; \
+ cd include ; \
+ echo "ARCH = arm" > config.mk ; \
+ echo "BOARD = samsung" >>config.mk ; \
+ echo "CPU = arm920t" >>config.mk ; \
+ echo "#include <configs/config_$(@:_config=).h>" >config.h
+
#########################################################################
clean:
rm -f armboot armboot.bin armboot.elf armboot.srec armboot.map
rm -f tools/crc32.c tools/environment.S
+mrproper \
distclean: clobber unconfig
backup:
--- /dev/null
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := samsung.o flash.o env.o
+SOBJS := memsetup.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm920t/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = ALIGN(4);
+ .bss : { *(.bss) }
+
+ armboot_end = .;
+}
--- /dev/null
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+#
+# SAMSUNG board with S3C2400X (arm920t) cpu
+#
+# see http://www.samsung.com/ for more information on SAMSUNG
+#
+
+#
+# SAMSUNG has 1 bank of 32 MB DRAM
+#
+# 0c00'0000 to 0e00'0000
+#
+# Linux-Kernel is expected to be at 0cf0'0000, entry 0cf0'0000
+# optionally with a ramdisk at 0c80'0000
+#
+# we load ourself to 0c17'0000
+#
+# download areas is 0c80'0000
+#
+
+
+TEXT_BASE = 0x0c170000
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "armboot.h"
+
+static int check_crc(bd_t *bd)
+{
+ /* need to calculate crc? */
+ if (bd->bi_ext.env_crc_valid == 0)
+ {
+ env_t *env = (env_t *)CFG_ENV_ADDR;
+
+ if (crc32(0, env->data, sizeof(env->data)) == env->crc)
+ bd->bi_ext.env_crc_valid = 1;
+ else
+ bd->bi_ext.env_crc_valid = -1;
+ }
+ return bd->bi_ext.env_crc_valid > 0;
+}
+
+
+/*
+ * save environment buffer back to flash
+ * returns -1 on error, 0 if ok
+ */
+int board_env_save(bd_t *bd, env_t *env, int size)
+{
+ int rc;
+ ulong start_addr, end_addr;
+
+#if CFG_ENV_SIZE <= CFG_ENV_SECT_SIZE
+#error Make sure that CFG_ENV_SIZE <= CFG_ENV_SECT_SIZE
+#endif
+
+ start_addr = CFG_ENV_ADDR;
+ end_addr = start_addr + CFG_ENV_SIZE - 1;
+
+ rc = flash_sect_protect(0, CFG_ENV_ADDR, end_addr);
+ if (rc < 0)
+ return rc;
+
+ rc = flash_sect_erase(start_addr, end_addr);
+ if (rc < 0)
+ {
+ flash_sect_protect(1, start_addr, end_addr);
+ flash_perror(rc);
+ return rc;
+ }
+
+ printf("Saving Environment to Flash...");
+ rc = flash_write((uchar*)env, start_addr, size);
+ if (rc < 0)
+ flash_perror(rc);
+ else
+ printf("done.\n");
+
+ (void)flash_sect_protect(1, start_addr, end_addr);
+
+ return 0;
+}
+
+/*
+ * copy environment to memory
+ * returns -1 on error, 0 if ok
+ */
+int board_env_copy(bd_t *bd, env_t *data, int size)
+{
+ env_t *env = (env_t *)CFG_ENV_ADDR;
+
+ if (check_crc(bd))
+ {
+ memcpy(data, env, sizeof(env_t));
+ return 0;
+ }
+
+ return -1;
+}
+
+/*
+ * try to read env character at offset #index
+ *
+ * called before the environment is copied to ram
+ * returns -1 on error, 0 if ok
+ */
+int board_env_getchar(bd_t * bd, int index, uchar *c)
+{
+ env_t *env = (env_t *)CFG_ENV_ADDR;
+
+ /* check environment crc */
+ if (index < sizeof(env->data) && check_crc(bd))
+ {
+ *c = env->data[index];
+ return 0;
+ }
+
+ return -1;
+}
+
+/*
+ * try to read env character at offset #index
+ *
+ * called before the environment is copied to ram
+ * returns -1 on error, 0 if ok
+ */
+uchar *board_env_getaddr(bd_t * bd, int index)
+{
+ env_t *env = (env_t *)CFG_ENV_ADDR;
+
+ /* check environment crc */
+ if (index < sizeof(env->data) && check_crc(bd))
+ return &env->data[index];
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "armboot.h"
+
+#define FLASH_BANK_SIZE 0x800000
+#define MAIN_SECT_SIZE 0x20000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+
+#define CMD_READ_ARRAY 0x00FF00FF
+#define CMD_IDENTIFY 0x00900090
+#define CMD_ERASE_SETUP 0x00200020
+#define CMD_ERASE_CONFIRM 0x00D000D0
+#define CMD_PROGRAM 0x00400040
+#define CMD_RESUME 0x00D000D0
+#define CMD_SUSPEND 0x00B000B0
+#define CMD_STATUS_READ 0x00700070
+#define CMD_STATUS_RESET 0x00500050
+
+#define BIT_BUSY 0x00800080
+#define BIT_ERASE_SUSPEND 0x00400040
+#define BIT_ERASE_ERROR 0x00200020
+#define BIT_PROGRAM_ERROR 0x00100010
+#define BIT_VPP_RANGE_ERROR 0x00080008
+#define BIT_PROGRAM_SUSPEND 0x00040004
+#define BIT_PROTECT_ERROR 0x00020002
+#define BIT_UNDEFINED 0x00010001
+
+#define BIT_SEQUENCE_ERROR 0x00300030
+#define BIT_TIMEOUT 0x80000000
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init(bd_t *bd)
+{
+ int i, j;
+ ulong size = 0;
+
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+ {
+ ulong flashbase = 0;
+ flash_info[i].flash_id =
+ (INTEL_MANUFACT & FLASH_VENDMASK) |
+ (INTEL_ID_28F640JA3 & FLASH_TYPEMASK);
+ flash_info[i].size = FLASH_BANK_SIZE;
+ flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+ memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+ if (i == 0)
+ flashbase = PHYS_FLASH_1;
+ else
+ panic("configured too many flash banks!\n");
+ for (j = 0; j < flash_info[i].sector_count; j++)
+ {
+ flash_info[i].start[j] = flashbase + j * MAIN_SECT_SIZE;
+ }
+ size += flash_info[i].size;
+ }
+
+ /* Protect monitor and environment sectors
+ */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE + _armboot_end - _armboot_start,
+ &flash_info[0]);
+
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+ &flash_info[0]);
+
+ return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ switch (info->flash_id & FLASH_VENDMASK)
+ {
+ case (INTEL_MANUFACT & FLASH_VENDMASK):
+ printf("Intel: ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK)
+ {
+ case (INTEL_ID_28F640JA3 & FLASH_TYPEMASK):
+ printf("2x 28F640JA3 (64Mbit)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ goto Done;
+ break;
+ }
+
+ printf(" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; i++)
+ {
+ if ((i % 5) == 0)
+ {
+ printf ("\n ");
+ }
+ printf (" %08lX%s", info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+
+Done:
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_error (ulong code)
+{
+ /* Check bit patterns */
+ /* SR.7=0 is busy, SR.7=1 is ready */
+ /* all other flags indicate error on 1 */
+ /* SR.0 is undefined */
+ /* Timeout is our faked flag */
+
+ /* sequence is described in Intel 290644-005 document */
+
+ /* check Timeout */
+ if (code & BIT_TIMEOUT)
+ {
+ printf ("Timeout\n");
+ return ERR_TIMOUT;
+ }
+
+ /* check Busy, SR.7 */
+ if (~code & BIT_BUSY)
+ {
+ printf ("Busy\n");
+ return ERR_PROG_ERROR;
+ }
+
+ /* check Vpp low, SR.3 */
+ if (code & BIT_VPP_RANGE_ERROR)
+ {
+ printf ("Vpp range error\n");
+ return ERR_PROG_ERROR;
+ }
+
+ /* check Device Protect Error, SR.1 */
+ if (code & BIT_PROTECT_ERROR)
+ {
+ printf ("Device protect error\n");
+ return ERR_PROG_ERROR;
+ }
+
+ /* check Command Seq Error, SR.4 & SR.5 */
+ if (code & BIT_SEQUENCE_ERROR)
+ {
+ printf ("Command seqence error\n");
+ return ERR_PROG_ERROR;
+ }
+
+ /* check Block Erase Error, SR.5 */
+ if (code & BIT_ERASE_ERROR)
+ {
+ printf ("Block erase error\n");
+ return ERR_PROG_ERROR;
+ }
+
+ /* check Program Error, SR.4 */
+ if (code & BIT_PROGRAM_ERROR)
+ {
+ printf ("Program error\n");
+ return ERR_PROG_ERROR;
+ }
+
+ /* check Block Erase Suspended, SR.6 */
+ if (code & BIT_ERASE_SUSPEND)
+ {
+ printf ("Block erase suspended\n");
+ return ERR_PROG_ERROR;
+ }
+
+ /* check Program Suspended, SR.2 */
+ if (code & BIT_PROGRAM_SUSPEND)
+ {
+ printf ("Program suspended\n");
+ return ERR_PROG_ERROR;
+ }
+
+ /* OK, no error */
+ return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ ulong result, result1;
+ int iflag, prot, sect;
+ int rc = ERR_OK;
+#ifdef USE_920T_MMU
+ int cflag;
+#endif
+
+ /* first look for protection bits */
+
+ if (info->flash_id == FLASH_UNKNOWN)
+ return ERR_UNKNOWN_FLASH_TYPE;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ return ERR_INVAL;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) !=
+ (INTEL_MANUFACT & FLASH_VENDMASK)) {
+ return ERR_UNKNOWN_FLASH_VENDOR;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+ if (prot)
+ return ERR_PROTECTED;
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+#ifdef USE_920T_MMU
+ cflag = dcache_status();
+ dcache_disable();
+#endif
+ iflag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last && !ctrlc(); sect++)
+ {
+ printf("Erasing sector %2d ... ", sect);
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked();
+
+ if (info->protect[sect] == 0)
+ { /* not protected */
+ vulong *addr = (vulong *)(info->start[sect]);
+ ulong bsR7, bsR7_2, bsR5, bsR5_2;
+
+ /* *addr = CMD_STATUS_RESET; */
+ *addr = CMD_ERASE_SETUP;
+ *addr = CMD_ERASE_CONFIRM;
+
+ /* wait until flash is ready */
+ do
+ {
+ /* check timeout */
+ if (get_timer_masked() > CFG_FLASH_ERASE_TOUT)
+ {
+ *addr = CMD_STATUS_RESET;
+ result = BIT_TIMEOUT;
+ break;
+ }
+
+ *addr = CMD_STATUS_READ;
+ result = *addr;
+ bsR7 = result & (1 << 7);
+ bsR7_2 = result & (1 << 23);
+ } while (!bsR7 | !bsR7_2);
+
+ *addr = CMD_STATUS_READ;
+ result1 = *addr;
+ bsR5 = result1 & (1 << 5);
+ bsR5_2 = result1 & (1 << 21);
+ printf("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2);
+ if (bsR5 != 0 && bsR5_2 != 0)
+ printf("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2);
+
+ *addr = CMD_READ_ARRAY;
+ *addr = CMD_RESUME;
+
+ if ((rc = flash_error(result)) != ERR_OK)
+ goto outahere;
+
+ printf("ok.\n");
+ }
+ else /* it was protected */
+ {
+ printf("protected!\n");
+ }
+ }
+
+ if (ctrlc())
+ printf("User Interrupt!\n");
+
+outahere:
+ /* allow flash to settle - wait 10 ms */
+ udelay_masked(10000);
+
+ if (iflag)
+ enable_interrupts();
+
+#ifdef USE_920T_MMU
+ if (cflag)
+ dcache_enable();
+#endif
+
+ return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+volatile static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ vulong *addr = (vulong *)dest;
+ ulong result;
+ int rc = ERR_OK;
+ int iflag;
+#ifdef USE_920T_MMU
+ int cflag;
+#endif
+
+ /* Check if Flash is (sufficiently) erased
+ */
+ result = *addr;
+ if ((result & data) != data)
+ return ERR_NOT_ERASED;
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+#ifdef USE_920T_MMU
+ cflag = dcache_status();
+ dcache_disable();
+#endif
+ iflag = disable_interrupts();
+
+ /* *addr = CMD_STATUS_RESET; */
+ *addr = CMD_PROGRAM;
+ *addr = data;
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked();
+
+ /* wait until flash is ready */
+ do
+ {
+ /* check timeout */
+ if (get_timer_masked() > CFG_FLASH_ERASE_TOUT)
+ {
+ *addr = CMD_SUSPEND;
+ result = BIT_TIMEOUT;
+ break;
+ }
+
+ *addr = CMD_STATUS_READ;
+ result = *addr;
+ } while (~result & BIT_BUSY);
+
+ /* *addr = CMD_READ_ARRAY; */
+ *addr = CMD_STATUS_READ;
+ result = *addr;
+
+ rc = flash_error(result);
+
+ if (iflag)
+ enable_interrupts();
+
+#ifdef USE_920T_MMU
+ if (cflag)
+ dcache_enable();
+#endif
+ *addr = CMD_READ_ARRAY;
+ *addr = CMD_RESUME;
+ return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int l;
+ int i, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data >> 8) | (*(uchar *)cp << 24);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data >> 8) | (*src++ << 24);
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data >> 8) | (*(uchar *)cp << 24);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = *((vulong*)src);
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ src += 4;
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return ERR_OK;
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data >> 8) | (*src++ << 24);
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data >> 8) | (*(uchar *)cp << 24);
+ }
+
+ return write_word(info, wp, data);
+}
--- /dev/null
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung development board by
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+
+#include "config.h"
+#include "version.h"
+
+
+/* some parameters for the board */
+
+/*
+ *
+ * Taken from linux/arch/arm/boot/compressed/head-s3c2400.S
+ *
+ * Copyright (C) 2001 Samsung Electronics by chc, 010406
+ *
+ * S3C2400 specific tweaks.
+ *
+ */
+
+// memory controller
+#define BWSCON 0x14000000
+#define BANKCON3 0x14000010 /* for cs8900, ethernet */
+
+// Bank0
+#define B0_Tacs 0x0 // 0 clk
+#define B0_Tcos 0x0 // 0 clk
+#define B0_Tacc 0x7 // 14 clk
+#define B0_Tcoh 0x0 // 0 clk
+#define B0_Tah 0x0 // 0 clk
+#define B0_Tacp 0x0
+#define B0_PMC 0x0 // normal
+
+// Bank1
+#define B1_Tacs 0x0 // 0 clk
+#define B1_Tcos 0x0 // 0 clk
+#define B1_Tacc 0x7 // 14 clk
+#define B1_Tcoh 0x0 // 0 clk
+#define B1_Tah 0x0 // 0 clk
+#define B1_Tacp 0x0
+#define B1_PMC 0x0 // normal
+
+// Bank2
+#define B2_Tacs 0x0 // 0 clk
+#define B2_Tcos 0x0 // 0 clk
+#define B2_Tacc 0x7 // 14 clk
+#define B2_Tcoh 0x0 // 0 clk
+#define B2_Tah 0x0 // 0 clk
+#define B2_Tacp 0x0
+#define B2_PMC 0x0 // normal
+
+// Bank3 - setup for the cs8900
+#define B3_Tacs 0x0 // 0 clk
+#define B3_Tcos 0x3 // 4 clk
+#define B3_Tacc 0x7 // 14 clk
+#define B3_Tcoh 0x1 // 1 clk
+#define B3_Tah 0x0 // 0 clk
+#define B3_Tacp 0x3 // 6 clk
+#define B3_PMC 0x0 // normal
+
+// Bank4
+#define B4_Tacs 0x0 // 0 clk
+#define B4_Tcos 0x0 // 0 clk
+#define B4_Tacc 0x7 // 14 clk
+#define B4_Tcoh 0x0 // 0 clk
+#define B4_Tah 0x0 // 0 clk
+#define B4_Tacp 0x0
+#define B4_PMC 0x0 // normal
+
+// Bank5
+#define B5_Tacs 0x0 // 0 clk
+#define B5_Tcos 0x0 // 0 clk
+#define B5_Tacc 0x7 // 14 clk
+#define B5_Tcoh 0x0 // 0 clk
+#define B5_Tah 0x0 // 0 clk
+#define B5_Tacp 0x0
+#define B5_PMC 0x0 // normal
+
+// Bank6
+#define B6_MT 0x3 // SDRAM
+#define B6_Trcd 0x1 // 3clk
+#define B6_SCAN 0x1 // 9 bit
+
+// Bank7
+#define B7_MT 0x3 // SDRAM
+#define B7_Trcd 0x1 // 3clk
+#define B7_SCAN 0x1 // 9 bit
+
+// refresh parameter
+#define REFEN 0x1 // enable refresh
+#define TREFMD 0x0 // CBR(CAS before RAS)/auto refresh
+#define Trp 0x0 // 2 clk
+#define Trc 0x3 // 7 clk
+#define Tchr 0x2 // 3 clk
+
+#define REFCNT 1113 // period=15.6 us, HCLK=60Mhz, (2048+1-15.6*66)
+
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl memsetup
+memsetup:
+ /* memory control configuration */
+ /* make r0 relative the current location so that it */
+ /* reads SMRDATA out of FLASH rather than memory ! */
+ ldr r0, =SMRDATA
+ ldr r1, _TEXT_BASE
+ sub r0, r0, r1
+ ldr r1, =BWSCON // Bus Width Status Controller
+ add r2, r0, #52
+0:
+ ldr r3, [r0], #4
+ str r3, [r1], #4
+ cmp r2, r0
+ bne 0b
+
+ /* everything is fine now */
+ mov pc, lr
+
+ .ltorg
+// the literal pools origin
+
+SMRDATA:
+ .word 0x2211d114 // d->Ethernet, BUSWIDTH=32
+ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) // GCS0
+ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) // GCS1
+ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) // GCS2
+ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) // GCS3
+ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) // GCS4
+ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) // GCS5
+ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) // GCS6
+ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) // GCS7
+ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+ .word 0x10 // BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M
+ .word 0x30 // MRSR6, CL=3clk
+ .word 0x30 // MRSR7
+
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "armboot.h"
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init(bd_t *bd)
+{
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of SAMSUNG-Board */
+ /* I have no idea what this means, so I just picked an unused value */
+ bd->bi_arch_number = 28;
+
+ /* adress of boot parameters */
+ bd->bi_boot_params = 0x0c000100;
+
+ return 1;
+}
+
+int dram_init(bd_t *bd)
+{
+ bd->bi_dram[0].start = PHYS_SDRAM_1;
+ bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ return PHYS_SDRAM_1_SIZE;
+}
#
#
-# LART has 4 banks of 8 MB DRAM
+# Tuxscreen has 4 banks of 4 MB DRAM each
#
# c000'0000
-# c100'0000
# c800'0000
-# c900'0000
+# d000'0000
+# d800'0000
#
# Linux-Kernel is expected to be at c000'8000, entry c000'8000
#
-# we load ourself to c170'0000, the upper 1 MB of second bank
+# we load ourself to d830'0000, the upper 1 MB of the last (4th) bank
#
# download areas is c800'0000
#
-TEXT_BASE = 0xc1700000
+TEXT_BASE = 0xd8300000
--- /dev/null
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(CPU).a
+
+START = start.o
+OBJS = serial.o interrupts.o cpu.o
+
+all: .depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common \
+ -mshort-load-bytes -msoft-float
+
+PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include "armboot.h"
+#include "command.h"
+#include "arm920t.h"
+
+/* it makes no sense to use the caches if the MMU also isn't used */
+#ifdef USE_920T_MMU
+/* read co-processor 15, register #1 (control register) */
+static unsigned long read_p15_c1(void)
+{
+ unsigned long value;
+
+ __asm__ __volatile__(
+ "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
+ : "=r" (value)
+ :
+ : "memory");
+ printf("p15/c1 is = %08lx\n", value);
+ return value;
+}
+
+/* write to co-processor 15, register #1 (control register) */
+static void write_p15_c1(unsigned long value)
+{
+ printf("write %08lx to p15/c1\n", value);
+ __asm__ __volatile__(
+ "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
+ : "=r" (value)
+ :
+ : "memory");
+ read_p15_c1();
+}
+
+static void cp_delay(void)
+{
+ volatile int i;
+
+ /* copro seems to need some delay between reading and writing */
+ for (i=0; i<100; i++);
+}
+
+/* See also ARM Ref. Man. */
+#define C1_MMU (1<<0) /* mmu off/on */
+#define C1_ALIGN (1<<1) /* alignment faults off/on */
+#define C1_DC (1<<2) /* dcache off/on */
+#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
+#define C1_SYS_PROT (1<<8) /* system protection */
+#define C1_ROM_PROT (1<<9) /* ROM protection */
+#define C1_IC (1<<12) /* icache off/on */
+#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
+#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */
+#endif
+
+void cpu_init(bd_t *bd)
+{
+ /*
+ * setup up stack if necessary
+ */
+#ifdef CONFIG_USE_IRQ
+ IRQ_STACK_START = _armboot_end +
+ CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4;
+ FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ;
+ _armboot_real_end = FIQ_STACK_START + 4;
+#else
+ _armboot_real_end = _armboot_end + CONFIG_STACKSIZE;
+#endif
+ /* change the clock to be 50 MHz 1:1:1 */
+ rMPLLCON = 0x5c042;
+ rCLKDIVN = 0;
+ /* set up the I/O ports */
+ rPACON = 0x3ffff;
+ rPBCON=0xaaaaaaaa;
+ rPBUP=0xffff;
+ rPECON=0x0;
+ rPEUP=0x0;
+ //INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0]
+ // 00, 00, 00, 00, 10, 00, 10
+ rPFCON=0x22;
+ rPFUP=0x5;
+ rPGCON=0x0;
+ rPGUP=0x0;
+ rOPENCR=0x0;
+}
+
+void cleanup_before_linux(bd_t *bd)
+{
+ /*
+ * this function is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we turn off caches etc ...
+ */
+
+#ifdef USE_920T_MMU
+ unsigned long i;
+#endif
+
+ disable_interrupts();
+
+#ifdef USE_920T_MMU
+ /* turn off I/D-cache */
+ asm ("mrc p15, 0, %0, c1, c0, 0": "=r" (i));
+ i &= ~(C1_DC|C1_IC);
+ asm ("mcr p15, 0, %0, c1, c0, 0": : "r" (i));
+
+ /* flush I/D-cache */
+ i = 0;
+ asm ("mcr p15, 0, %0, c7, c7, 0": : "r" (i));
+#endif
+
+}
+
+void do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ extern void reset_cpu(ulong addr);
+
+ disable_interrupts();
+ reset_cpu(0);
+ /*NOTREACHED*/
+}
+
+#ifdef USE_920T_MMU
+void icache_enable(void)
+{
+ ulong reg;
+ reg = read_p15_c1();
+ cp_delay();
+ write_p15_c1(reg | C1_IC);
+}
+
+void icache_disable(void)
+{
+ ulong reg;
+ reg = read_p15_c1();
+ cp_delay();
+ write_p15_c1(reg & ~C1_IC);
+}
+
+int icache_status(void)
+{
+ return (read_p15_c1() & C1_IC) != 0;
+}
+
+void dcache_enable(void)
+{
+ ulong reg;
+ reg = read_p15_c1();
+ cp_delay();
+ write_p15_c1(reg | C1_DC);
+}
+
+void dcache_disable(void)
+{
+ ulong reg;
+ reg = read_p15_c1();
+ cp_delay();
+ reg &= ~C1_DC;
+ write_p15_c1(reg);
+}
+
+int dcache_status(void)
+{
+ return (read_p15_c1() & C1_DC) != 0;
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "armboot.h"
+#include "arm920t.h"
+#include "ptregs.h"
+
+extern void reset_cpu(ulong addr);
+
+/* for 10 ms clock period @ 50 MHz with 4 bit divider = 1/2 (default) */
+/* and prescaler = 16 */
+#define TIMER_LOAD_VAL 15625
+
+/* macro to read the 16 bit timer */
+#define READ_TIMER (rTCNTO4 & 0xffff)
+
+#ifdef CONFIG_USE_IRQ
+/* enable IRQ interrupts */
+void enable_interrupts (void)
+{
+ unsigned long temp;
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ "bic %0, %0, #0x80\n"
+ "msr cpsr_c, %0"
+ : "=r" (temp)
+ :
+ : "memory");
+}
+
+
+/*
+ * disable IRQ/FIQ interrupts
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts (void)
+{
+ unsigned long old,temp;
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ "orr %1, %0, #0xc0\n"
+ "msr cpsr_c, %1"
+ : "=r" (old), "=r" (temp)
+ :
+ : "memory");
+ return (old & 0x80) == 0;
+}
+#else
+void enable_interrupts (void)
+{
+ return;
+}
+int disable_interrupts (void)
+{
+ return 0;
+}
+#endif
+
+
+
+void bad_mode(void)
+{
+ panic("Resetting CPU ...\n");
+ reset_cpu(0);
+}
+
+void show_regs(struct pt_regs * regs)
+{
+ unsigned long flags;
+const char *processor_modes[]=
+{ "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" ,
+ "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26",
+ "USER_32", "FIQ_32" , "IRQ_32" , "SVC_32" , "UK4_32" , "UK5_32" , "UK6_32" , "ABT_32" ,
+ "UK8_32" , "UK9_32" , "UK10_32", "UND_32" , "UK12_32", "UK13_32", "UK14_32", "SYS_32"
+};
+
+ flags = condition_codes(regs);
+
+ printf("pc : [<%08lx>] lr : [<%08lx>]\n"
+ "sp : %08lx ip : %08lx fp : %08lx\n",
+ instruction_pointer(regs),
+ regs->ARM_lr, regs->ARM_sp,
+ regs->ARM_ip, regs->ARM_fp);
+ printf("r10: %08lx r9 : %08lx r8 : %08lx\n",
+ regs->ARM_r10, regs->ARM_r9,
+ regs->ARM_r8);
+ printf("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
+ regs->ARM_r7, regs->ARM_r6,
+ regs->ARM_r5, regs->ARM_r4);
+ printf("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
+ regs->ARM_r3, regs->ARM_r2,
+ regs->ARM_r1, regs->ARM_r0);
+ printf("Flags: %c%c%c%c",
+ flags & CC_N_BIT ? 'N' : 'n',
+ flags & CC_Z_BIT ? 'Z' : 'z',
+ flags & CC_C_BIT ? 'C' : 'c',
+ flags & CC_V_BIT ? 'V' : 'v');
+ printf(" IRQs %s FIQs %s Mode %s%s\n",
+ interrupts_enabled(regs) ? "on" : "off",
+ fast_interrupts_enabled(regs) ? "on" : "off",
+ processor_modes[processor_mode(regs)],
+ thumb_mode(regs) ? " (T)" : "");
+}
+
+void do_undefined_instruction(struct pt_regs *pt_regs)
+{
+ printf("undefined instruction\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_software_interrupt(struct pt_regs *pt_regs)
+{
+ printf("software interrupt\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_prefetch_abort(struct pt_regs *pt_regs)
+{
+ printf("prefetch abort\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_data_abort(struct pt_regs *pt_regs)
+{
+ printf("data abort\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_not_used(struct pt_regs *pt_regs)
+{
+ printf("not used\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_fiq(struct pt_regs *pt_regs)
+{
+ printf("fast interrupt request\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_irq(struct pt_regs *pt_regs)
+{
+ printf("interrupt request\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+static ulong timestamp;
+static ulong lastdec;
+
+extern void interrupt_init (bd_t *bd)
+{
+ /* use PWM Timer 4 because it has no output */
+ /* prescaler for Timer 4 is 16 */
+ rTCFG0 = 0x0f00;
+ /* load value for 10 ms timeout, assumes PCLK is 30 MHz !! */
+ lastdec = rTCNTB4 = TIMER_LOAD_VAL;
+ /* auto load, manual update of Timer 4 */
+ rTCON = 0x600000;
+ /* auto load, start Timer 4 */
+ rTCON = 0x500000;
+ timestamp = 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer (ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer (ulong t)
+{
+ timestamp = t;
+}
+
+void udelay(unsigned long usec)
+{
+ ulong tmo;
+
+ tmo = usec / 1000;
+ tmo *= CFG_HZ;
+ tmo /= 1000;
+
+ tmo += get_timer(0);
+
+ while(get_timer_masked() < tmo)
+ /*NOP*/;
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ lastdec = READ_TIMER;
+ timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+ ulong now = READ_TIMER;
+
+ if (lastdec >= now)
+ {
+ /* normal mode */
+ timestamp += lastdec - now;
+ } else {
+ /* we have an overflow ... */
+ timestamp += lastdec + TIMER_LOAD_VAL - now;
+ }
+ lastdec = now;
+
+ return timestamp;
+}
+
+void udelay_masked(unsigned long usec)
+{
+ ulong tmo;
+
+ tmo = usec / 1000;
+ tmo *= CFG_HZ;
+ tmo /= 1000;
+
+ reset_timer_masked();
+
+ while(get_timer_masked() < tmo)
+ /*NOP*/;
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include "armboot.h"
+#include "arm920t.h"
+
+unsigned int br[] = {1562, 780, 390, 194, 32, 15};
+void serial_setbrg(bd_t *bd, int baudrate)
+{
+ int i;
+ unsigned int reg = 0;
+
+ /* this assumes a PCLK of 50 MHz */
+ /* value is calculated so : (int)(PCLK/16./baudrate) -1 */
+ if (baudrate == 1200) reg = 2603;
+ else if (baudrate == 9600) reg = 325;
+ else if (baudrate == 19200) reg = 162;
+ else if (baudrate == 38400) reg = 80;
+ else if (baudrate == 57600) reg = 53;
+ else if (baudrate == 115200) reg = 26;
+ else hang();
+
+#ifdef CONFIG_SERIAL1
+ rUFCON0=0x0;
+ rUMCON0=0x0;
+ /* Normal,No parity,1 stop,8 bit */
+ rULCON0=0x3;
+ /*
+ * tx=level,rx=edge,disable timeout int.,enable rx error int.,
+ * normal,interrupt or polling
+ */
+ rUCON0=0x245;
+ rUBRDIV0 = reg;
+
+ for(i=0;i<100;i++);
+#elif CONFIG_SERIAL2
+ rUFCON1=0x0;
+ rUMCON1=0x0;
+ /* Normal,No parity,1 stop,8 bit */
+ rULCON1=0x3;
+ /*
+ * tx=level,rx=edge,disable timeout int.,enable rx error int.,
+ * normal,interrupt or polling
+ */
+ rUCON1=0x245;
+ rUBRDIV1 = reg;
+
+ for(i=0;i<100;i++);
+#else
+#error "Bad: you didn't configure serial ..."
+#endif
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ *
+ */
+void serial_init(bd_t *bd)
+{
+ const char *baudrate;
+
+ if ((baudrate = getenv(bd, "baudrate")) != 0)
+ bd->bi_baudrate = simple_strtoul(baudrate, NULL, 10);
+
+ serial_setbrg(bd, bd->bi_baudrate);
+}
+
+/*
+ * Read a single byte from the serial port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int serial_getc(void)
+{
+#ifdef CONFIG_SERIAL1
+ while(!(rUTRSTAT0 & 0x1))
+ ;
+
+ return rURXH0 & 0xff;
+#elif CONFIG_SERIAL2
+ while(!(rUTRSTAT1 & 0x1))
+ ;
+
+ return rURXH1 & 0xff;
+#endif
+}
+
+
+/*
+ * Output a single byte to the serial port.
+ */
+void serial_putc(const char c)
+{
+#ifdef CONFIG_SERIAL1
+ /* wait for room in the tx FIFO on SERIAL1 */
+ while(!(rUTRSTAT0 & 0x2))
+ ;
+
+ rUTXH0 = c;
+#elif CONFIG_SERIAL2
+ /* wait for room in the tx FIFO on SERIAL2 */
+ while(!(rUTRSTAT1 & 0x2))
+ ;
+
+ rUTXH1= c;
+#endif
+
+ /* If \n, also do \r */
+ if(c == '\n')
+ serial_putc('\r');
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+int serial_tstc(void)
+{
+#ifdef CONFIG_SERIAL1
+ return rUTRSTAT0 & 0x1;
+#elif CONFIG_SERIAL2
+ return rUTRSTAT1 & 0x1;
+#endif
+}
+
--- /dev/null
+/*
+ * armboot - Startup Code for ARM920 CPU-core
+ *
+ * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
+ * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
+ * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+
+#include "config.h"
+#include "version.h"
+
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+
+.globl _start
+_start: b reset
+ ldr pc, _undefined_instruction
+ ldr pc, _software_interrupt
+ ldr pc, _prefetch_abort
+ ldr pc, _data_abort
+ ldr pc, _not_used
+ ldr pc, _irq
+ ldr pc, _fiq
+
+_undefined_instruction: .word undefined_instruction
+_software_interrupt: .word software_interrupt
+_prefetch_abort: .word prefetch_abort
+_data_abort: .word data_abort
+_not_used: .word not_used
+_irq: .word irq
+_fiq: .word fiq
+
+ .balignl 16,0xdeadbeef
+
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * relocate armboot to ram
+ * setup stack
+ * jump to second stage
+ *
+ *************************************************************************
+ */
+
+/*
+ * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
+ */
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl _armboot_start
+_armboot_start:
+ .word _start
+
+/*
+ * Note: armboot_end is defined by the (board-dependent) linker script
+ */
+.globl _armboot_end
+_armboot_end:
+ .word armboot_end
+
+/*
+ * _armboot_real_end is the first usable RAM address behind armboot
+ * and the various stacks
+ */
+.globl _armboot_real_end
+_armboot_real_end:
+ .word 0x0badc0de
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+ .word 0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+ .word 0x0badc0de
+#endif
+
+
+/*
+ * the actual reset code
+ */
+
+reset:
+ /*
+ * set the cpu to SVC32 mode
+ */
+ mrs r0,cpsr
+ bic r0,r0,#0x1f
+ orr r0,r0,#0xd3
+ msr cpsr,r0
+
+/* turn off the watchdog */
+#define pWTCON 0x15300000
+/* Interupt-Controller base addresses */
+#define INTMR 0x14400008
+/* clock divisor register */
+#define CLKDIVN 0x14800014
+
+ ldr r0, =pWTCON
+ mov r1, #0x0
+ str r1, [r0]
+
+ /*
+ * mask all IRQs by setting all bits in the INTMR - default
+ */
+ mov r1, #0xffffffff
+ ldr r0, =INTMR
+ str r1, [r0]
+
+ /* FCLK:HCLK:PCLK = 1:2:4 */
+ /* default FCLK is 120 MHz ! */
+ ldr r0, =CLKDIVN
+ mov r1, #3
+ str r1, [r0]
+
+ /*
+ * we do sys-critical inits only at reboot,
+ * not when booting from ram!
+ */
+#ifdef CONFIG_INIT_CRITICAL
+ bl cpu_init_crit
+#endif
+
+relocate:
+ /*
+ * relocate armboot to RAM
+ */
+ adr r0, _start /* r0 <- current position of code */
+ ldr r2, _armboot_start
+ ldr r3, _armboot_end
+ sub r2, r3, r2 /* r2 <- size of armboot */
+ ldr r1, _TEXT_BASE /* r1 <- destination address */
+ add r2, r0, r2 /* r2 <- source end address */
+
+ /*
+ * r0 = source address
+ * r1 = target address
+ * r2 = source end address
+ */
+copy_loop:
+ ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ ble copy_loop
+
+#if 0
+ /* try doing this stuff after the relocation */
+ ldr r0, =pWTCON
+ mov r1, #0x0
+ str r1, [r0]
+
+ /*
+ * mask all IRQs by setting all bits in the INTMR - default
+ */
+ mov r1, #0xffffffff
+ ldr r0, =INTMR
+ str r1, [r0]
+
+ /* FCLK:HCLK:PCLK = 1:2:4 */
+ /* default FCLK is 120 MHz ! */
+ ldr r0, =CLKDIVN
+ mov r1, #3
+ str r1, [r0]
+ /* END stuff after relocation */
+#endif
+
+ /* set up the stack */
+ ldr r0, _armboot_end
+ add r0, r0, #CONFIG_STACKSIZE
+ sub sp, r0, #12 /* leave 3 words for abort-stack */
+
+ ldr pc, _start_armboot
+
+_start_armboot: .word start_armboot
+
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+
+
+cpu_init_crit:
+ /*
+ * flush v4 I/D caches
+ */
+ mov r0, #0
+ mcr p15, 0, r0, c7, c7, 0 // flush v3/v4 cache
+ mcr p15, 0, r0, c8, c7, 0 // flush v4 TLB
+
+ /*
+ * disable MMU stuff and caches
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
+ bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
+ orr r0, r0, #0x00000002 @ set bit 2 (A) Align
+ mcr p15, 0, r0, c1, c0, 0
+
+
+ /*
+ * before relocating, we have to setup RAM timing
+ * because memory timing is board-dependend, you will
+ * find a memsetup.S in your board directory.
+ */
+ mov ip, lr
+ bl memsetup
+ mov lr, ip
+
+ mov pc, lr
+
+
+
+
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE 72
+
+#define S_OLD_R0 68
+#define S_PSR 64
+#define S_PC 60
+#define S_LR 56
+#define S_SP 52
+
+#define S_IP 48
+#define S_FP 44
+#define S_R10 40
+#define S_R9 36
+#define S_R8 32
+#define S_R7 28
+#define S_R6 24
+#define S_R5 20
+#define S_R4 16
+#define S_R3 12
+#define S_R2 8
+#define S_R1 4
+#define S_R0 0
+
+#define MODE_SVC 0x13
+#define I_BIT 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+ .macro bad_save_user_regs
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} @ Calling r0-r12
+ add r8, sp, #S_PC
+
+ ldr r2, _armboot_end
+ add r2, r2, #CONFIG_STACKSIZE
+ sub r2, r2, #8
+ ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
+ add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
+
+ add r5, sp, #S_SP
+ mov r1, lr
+ stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
+ mov r0, sp
+ .endm
+
+ .macro irq_save_user_regs
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} @ Calling r0-r12
+ add r8, sp, #S_PC
+ stmdb r8, {sp, lr}^ @ Calling SP, LR
+ str lr, [r8, #0] @ Save calling PC
+ mrs r6, spsr
+ str r6, [r8, #4] @ Save CPSR
+ str r0, [r8, #8] @ Save OLD_R0
+ mov r0, sp
+ .endm
+
+ .macro irq_restore_user_regs
+ ldmia sp, {r0 - lr}^ @ Calling r0 - lr
+ mov r0, r0
+ ldr lr, [sp, #S_PC] @ Get PC
+ add sp, sp, #S_FRAME_SIZE
+ subs pc, lr, #4 @ return & move spsr_svc into cpsr
+ .endm
+
+ .macro get_bad_stack
+ ldr r13, _armboot_end @ setup our mode stack
+ add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
+ sub r13, r13, #8
+
+ str lr, [r13] @ save caller lr / spsr
+ mrs lr, spsr
+ str lr, [r13, #4]
+
+ mov r13, #MODE_SVC @ prepare SVC-Mode
+ @ msr spsr_c, r13
+ msr spsr, r13
+ mov lr, pc
+ movs pc, lr
+ .endm
+
+ .macro get_irq_stack @ setup IRQ stack
+ ldr sp, IRQ_STACK_START
+ .endm
+
+ .macro get_fiq_stack @ setup FIQ stack
+ ldr sp, FIQ_STACK_START
+ .endm
+
+/*
+ * exception handlers
+ */
+ .align 5
+undefined_instruction:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_undefined_instruction
+
+ .align 5
+software_interrupt:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_software_interrupt
+
+ .align 5
+prefetch_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_prefetch_abort
+
+ .align 5
+data_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_data_abort
+
+ .align 5
+not_used:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+ .align 5
+irq:
+ get_irq_stack
+ irq_save_user_regs
+ bl do_irq
+ irq_restore_user_regs
+
+ .align 5
+fiq:
+ get_fiq_stack
+ /* someone ought to write a more effiction fiq_save_user_regs */
+ irq_save_user_regs
+ bl do_fiq
+ irq_restore_user_regs
+
+#else
+
+ .align 5
+irq:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_irq
+
+ .align 5
+fiq:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_fiq
+
+#endif
+
+ .align 5
+.globl reset_cpu
+reset_cpu:
+ mov ip, #0
+ mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
+ mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
+ mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
+ bic ip, ip, #0x000f @ ............wcam
+ bic ip, ip, #0x2100 @ ..v....s........
+ mcr p15, 0, ip, c1, c0, 0 @ ctrl register
+ mov pc, r0
--- /dev/null
+/*------------------------------------------------------------------------
+ . smc91111.c
+ . This is a driver for SMSC's 91C111 single-chip Ethernet device.
+ .
+ . (C) Copyright 2002
+ . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ . Rolf Offermanns <rof@sysgo.de>
+ .
+ . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
+ . Developed by Simple Network Magic Corporation (SNMC)
+ . Copyright (C) 1996 by Erik Stahlman (ES)
+ .
+ . This program is free software; you can redistribute it and/or modify
+ . it under the terms of the GNU General Public License as published by
+ . the Free Software Foundation; either version 2 of the License, or
+ . (at your option) any later version.
+ .
+ . This program is distributed in the hope that it will be useful,
+ . but WITHOUT ANY WARRANTY; without even the implied warranty of
+ . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ . GNU General Public License for more details.
+ .
+ . You should have received a copy of the GNU General Public License
+ . along with this program; if not, write to the Free Software
+ . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ .
+ . Information contained in this file was obtained from the LAN91C111
+ . manual from SMC. To get a copy, if you really want one, you can find
+ . information under www.smsc.com.
+ .
+ .
+ . "Features" of the SMC chip:
+ . Integrated PHY/MAC for 10/100BaseT Operation
+ . Supports internal and external MII
+ . Integrated 8K packet memory
+ . EEPROM interface for configuration
+ .
+ . Arguments:
+ . io = for the base address
+ . irq = for the IRQ
+ .
+ . author:
+ . Erik Stahlman ( erik@vt.edu )
+ . Daris A Nevil ( dnevil@snmc.com )
+ .
+ .
+ . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
+ .
+ . Sources:
+ . o SMSC LAN91C111 databook (www.smsc.com)
+ . o smc9194.c by Erik Stahlman
+ . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
+ .
+ . History:
+ . 10/17/01 Marco Hasewinkel Modify for DNP/1110
+ . 07/25/01 Woojung Huh Modify for ADS Bitsy
+ . 04/25/01 Daris A Nevil Initial public release through SMSC
+ . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
+ ----------------------------------------------------------------------------*/
+
+#include "armboot.h"
+#include "command.h"
+#include "net.h"
+
+#ifdef CONFIG_DRIVER_3C589
+
+#include "3c589.h"
+
+
+// Use power-down feature of the chip
+#define POWER_DOWN 0
+
+#define NO_AUTOPROBE
+
+static const char version[] =
+ "Your ad here! :P\n";
+
+
+#undef EL_DEBUG
+
+typedef unsigned char byte;
+typedef unsigned short word;
+typedef unsigned long int dword;
+/*------------------------------------------------------------------------
+ .
+ . Configuration options, for the experienced user to change.
+ .
+ -------------------------------------------------------------------------*/
+
+/*
+ . Wait time for memory to be free. This probably shouldn't be
+ . tuned that much, as waiting for this means nothing else happens
+ . in the system
+*/
+#define MEMORY_WAIT_TIME 16
+
+
+#if (EL_DEBUG > 2 )
+#define PRINTK3(args...) printf(args)
+#else
+#define PRINTK3(args...)
+#endif
+
+#if EL_DEBUG > 1
+#define PRINTK2(args...) printf(args)
+#else
+#define PRINTK2(args...)
+#endif
+
+#ifdef EL_DEBUG
+#define PRINTK(args...) printf(args)
+#else
+#define PRINTK(args...)
+#endif
+
+#define outb(args...) mmio_outb(args)
+#define mmio_outb(value, addr) (*((volatile byte *)(addr)) = value)
+
+#define inb(args...) mmio_inb(args)
+#define mmio_inb(addr) (*((volatile byte *)(addr)))
+
+#define outw(args...) mmio_outw(args)
+#define mmio_outw(value, addr) (*((volatile word *)(addr)) = value)
+
+#define inw(args...) mmio_inw(args)
+#define mmio_inw(addr) (*((volatile word *)(addr)))
+
+#define outsw(args...) mmio_outsw(args)
+#define mmio_outsw(r,b,l) ({ int __i; \
+ word *__b2; \
+ __b2 = (word *) b; \
+ for (__i = 0; __i < l; __i++) { \
+ mmio_outw( *(__b2 + __i), r); \
+ } \
+ })
+
+#define insw(args...) mmio_insw(args)
+#define mmio_insw(r,b,l) ({ int __i ; \
+ word *__b2; \
+ __b2 = (word *) b; \
+ for (__i = 0; __i < l; __i++) { \
+ *(__b2 + __i) = mmio_inw(r); \
+ mmio_inw(0); \
+ }; \
+ })
+
+/*------------------------------------------------------------------------
+ .
+ . The internal workings of the driver. If you are changing anything
+ . here with the SMC stuff, you should have the datasheet and know
+ . what you are doing.
+ .
+ -------------------------------------------------------------------------*/
+#define EL_BASE_ADDR 0x20000000
+
+
+/* Offsets from base I/O address. */
+#define EL3_DATA 0x00
+#define EL3_TIMER 0x0a
+#define EL3_CMD 0x0e
+#define EL3_STATUS 0x0e
+
+#define EEPROM_READ 0x0080
+
+#define EL3WINDOW(win_num) mmio_outw(SelectWindow + (win_num), EL_BASE_ADDR + EL3_CMD)
+
+/* The top five bits written to EL3_CMD are a command, the lower
+ 11 bits are the parameter, if applicable. */
+enum c509cmd {
+ TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
+ RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11, RxDiscard = 8<<11,
+ TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
+ FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
+ SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
+ SetTxThreshold = 18<<11, SetTxStart = 19<<11, StatsEnable = 21<<11,
+ StatsDisable = 22<<11, StopCoax = 23<<11,
+};
+
+enum c509status {
+ IntLatch = 0x0001, AdapterFailure = 0x0002, TxComplete = 0x0004,
+ TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
+ IntReq = 0x0040, StatsFull = 0x0080, CmdBusy = 0x1000
+};
+
+/* The SetRxFilter command accepts the following classes: */
+enum RxFilter {
+ RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8
+};
+
+/* Register window 1 offsets, the window used in normal operation. */
+#define TX_FIFO 0x00
+#define RX_FIFO 0x00
+#define RX_STATUS 0x08
+#define TX_STATUS 0x0B
+#define TX_FREE 0x0C /* Remaining free bytes in Tx buffer. */
+
+
+/*
+ Read a word from the EEPROM using the regular EEPROM access register.
+ Assume that we are in register window zero.
+*/
+static word read_eeprom(dword ioaddr, int index)
+{
+ int i;
+ outw(EEPROM_READ + index, ioaddr + 0xa);
+ /* Reading the eeprom takes 162 us */
+ for (i = 1620; i >= 0; i--)
+ if ((inw(ioaddr + 10) & EEPROM_BUSY) == 0)
+ break;
+ return inw(ioaddr + 0xc);
+}
+
+static void el_get_mac_addr( word *mac_addr )
+{
+ int i;
+ unsigned char old_window = inw( EL_BASE_ADDR + EL3_STATUS ) >> 13;
+ GO_WINDOW(0);
+ VX_BUSY_WAIT;
+ for (i = 0; i < 3; i++)
+ {
+ *(mac_addr+i) = read_eeprom(EL_BASE_ADDR, 0xa+i);
+ }
+ GO_WINDOW(old_window);
+ VX_BUSY_WAIT;
+}
+
+
+static void print_packet( byte * buf, int length )
+{
+ int i;
+ int remainder;
+ int lines;
+
+ PRINTK2("Packet of length %d \n", length );
+
+ lines = length / 16;
+ remainder = length % 16;
+
+ for ( i = 0; i < lines ; i ++ ) {
+ int cur;
+
+ for ( cur = 0; cur < 8; cur ++ ) {
+ byte a, b;
+
+ a = *(buf ++ );
+ b = *(buf ++ );
+ PRINTK2("%02x%02x ", a, b );
+ }
+ PRINTK2("\n");
+ }
+ for ( i = 0; i < remainder/2 ; i++ ) {
+ byte a, b;
+
+ a = *(buf ++ );
+ b = *(buf ++ );
+ PRINTK2("%02x%02x ", a, b );
+ }
+ PRINTK2("\n");
+}
+
+
+
+/**************************************************************************
+ETH_RESET - Reset adapter
+***************************************************************************/
+static void el_reset(bd_t *bd)
+{
+ /***********************************************************
+ Reset 3Com 595 card
+ *************************************************************/
+ /* QUICK HACK
+ * - adjust timing for 3c589
+ * - enable io for PCMCIA */
+ outw(0x0004, 0xa0000018);
+ udelay(100);
+ outw(0x0041, 0x28010000);
+ udelay(100);
+
+ /* issue global reset */
+ outw(GLOBAL_RESET, BASE + VX_COMMAND);
+
+ /* must wait for at least 1ms */
+ udelay(100000000);
+
+ /* set mac addr */
+/*
+ outw(0xfeca, BASE + VX_W2_ADDR_0);
+ VX_BUSY_WAIT;
+ outw(0xadde, BASE + VX_W2_ADDR_2);
+ VX_BUSY_WAIT;
+ outw(0xefbe, BASE + VX_W2_ADDR_4);
+ VX_BUSY_WAIT;
+*/
+ {
+ word *mac_addr = (word *)bd->bi_enetaddr;
+ int i;
+
+ el_get_mac_addr( mac_addr );
+
+ GO_WINDOW(2);
+ VX_BUSY_WAIT;
+
+ printf("3C589 MAC Addr.: ");
+ for (i = 0; i < 3; i++)
+ {
+ printf("%04x", mac_addr[i]);
+ outw(mac_addr[i], BASE + VX_W2_ADDR_0 + i*2);
+ VX_BUSY_WAIT;
+ }
+ printf("\n\n");
+ }
+
+ /* set RX filter */
+ outw(SET_RX_FILTER | FIL_INDIVIDUAL | FIL_BRDCST, BASE + VX_COMMAND);
+ VX_BUSY_WAIT;
+
+
+ /* set irq mask and read_zero */
+ outw(SET_RD_0_MASK | S_CARD_FAILURE | S_RX_COMPLETE |
+ S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND);
+ VX_BUSY_WAIT;
+
+ outw(SET_INTR_MASK | S_CARD_FAILURE | S_RX_COMPLETE |
+ S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND);
+ VX_BUSY_WAIT;
+
+ /* enable TP Linkbeat */
+ GO_WINDOW(4);
+ VX_BUSY_WAIT;
+
+ outw( ENABLE_UTP, BASE + VX_W4_MEDIA_TYPE);
+ VX_BUSY_WAIT;
+
+
+/*
+ * Attempt to get rid of any stray interrupts that occured during
+ * configuration. On the i386 this isn't possible because one may
+ * already be queued. However, a single stray interrupt is
+ * unimportant.
+ */
+
+ outw(ACK_INTR | 0xff, BASE + VX_COMMAND);
+ VX_BUSY_WAIT;
+
+ /* enable TX and RX */
+ outw( RX_ENABLE, BASE + VX_COMMAND );
+ VX_BUSY_WAIT;
+
+ outw( TX_ENABLE, BASE + VX_COMMAND );
+ VX_BUSY_WAIT;
+
+
+ /* print the diag. regs. */
+ PRINTK2("Diag. Regs\n");
+ PRINTK2("--> MEDIA_TYPE: %04x\n", inw(BASE + VX_W4_MEDIA_TYPE));
+ PRINTK2("--> NET_DIAG: %04x\n", inw(BASE + VX_W4_NET_DIAG));
+ PRINTK2("--> FIFO_DIAG: %04x\n", inw(BASE + VX_W4_FIFO_DIAG));
+ PRINTK2("--> CTRLR_STATUS: %04x\n", inw(BASE + VX_W4_CTRLR_STATUS));
+ PRINTK2("\n\n");
+
+ /* enter working mode */
+ GO_WINDOW(1);
+ VX_BUSY_WAIT;
+
+}
+
+
+/*-----------------------------------------------------------------
+ .
+ . The driver can be entered at any of the following entry points.
+ .
+ .------------------------------------------------------------------ */
+
+extern int eth_init(bd_t *bd);
+extern void eth_halt(void);
+extern int eth_rx(void);
+extern int eth_send(volatile void *packet, int length);
+
+
+/*
+ ------------------------------------------------------------
+ .
+ . Internal routines
+ .
+ ------------------------------------------------------------
+*/
+
+int eth_init(bd_t *bd)
+{
+ el_reset(bd);
+ return 0;
+}
+
+void eth_halt() {
+ return;
+}
+
+#define EDEBUG 1
+
+
+/**************************************************************************
+ETH_POLL - Wait for a frame
+***************************************************************************/
+
+int eth_rx()
+{
+ word status, rx_status, packet_size;
+
+ VX_BUSY_WAIT;
+
+ status = inw( BASE + VX_STATUS );
+
+ if ( (status & S_RX_COMPLETE) == 0 ) return 0; /* nothing to do */
+
+ /* Packet waiting -> check RX_STATUS */
+ rx_status = inw( BASE + VX_W1_RX_STATUS );
+
+ if ( rx_status & ERR_RX )
+ {
+ /* error in packet -> discard */
+ PRINTK("[ERROR] Invalid packet -> discarding\n");
+ outw( RX_DISCARD_TOP_PACK, BASE + VX_COMMAND );
+ return 0;
+ }
+
+ /* correct pack. waiting in fifo */
+ packet_size = rx_status & RX_BYTES_MASK;
+
+ PRINTK("Correct packet waiting in fifo, size: %d\n", packet_size);
+
+ {
+ volatile word *packet_start = (word *)(BASE + VX_W1_RX_PIO_RD_1);
+ word *RcvBuffer = (word *)(NetRxPackets[0]);
+ int wcount = 0;
+
+ for (wcount = 0; wcount < (packet_size >> 1); wcount++)
+ {
+ *RcvBuffer++ = *(packet_start);
+ }
+
+ /* handle odd packets */
+ if ( packet_size & 1 )
+ {
+ *RcvBuffer++ = *(packet_start);
+ }
+ }
+
+ /* fifo should now be empty (besides the padding bytes) */
+ if ( ((*((word *)(BASE + VX_W1_RX_STATUS))) & RX_BYTES_MASK) > 3 )
+ {
+ PRINTK("[ERROR] Fifo not empty after packet read (remaining pkts: %d)\n",
+ (((*(word *)(BASE + VX_W1_RX_STATUS))) & RX_BYTES_MASK));
+ }
+
+ /* discard packet */
+ *((word *)(BASE + VX_COMMAND)) = RX_DISCARD_TOP_PACK;
+
+ /* Pass Packets to upper Layer */
+ NetReceive(NetRxPackets[0], packet_size);
+ return packet_size;
+}
+
+
+
+/**************************************************************************
+ETH_TRANSMIT - Transmit a frame
+***************************************************************************/
+static char padmap[] = {
+ 0, 3, 2, 1};
+
+
+int eth_send(volatile void *packet, int length) {
+ int pad;
+ int status;
+ volatile word *buf = (word *)packet;
+ int dummy = 0;
+
+ /* padding stuff */
+ pad = padmap[length & 3];
+
+ PRINTK("eth_send(), length: %d\n", length);
+ /* drop acknowledgements */
+ while(( status=inb(EL_BASE_ADDR + VX_W1_TX_STATUS) )& TXS_COMPLETE ) {
+ if(status & (TXS_UNDERRUN|TXS_MAX_COLLISION|TXS_STATUS_OVERFLOW)) {
+ outw(TX_RESET, EL_BASE_ADDR + VX_COMMAND);
+ outw(TX_ENABLE, EL_BASE_ADDR + VX_COMMAND);
+ PRINTK("Bad status, resetting and reenabling transmitter\n");
+ }
+
+ outb(0x0, EL_BASE_ADDR + VX_W1_TX_STATUS);
+ }
+
+
+ while (inw(EL_BASE_ADDR + VX_W1_FREE_TX) < length + pad + 4) {
+ /* no room in FIFO */
+ if (dummy == 0)
+ {
+ PRINTK("No room in FIFO, waiting...\n");
+ dummy++;
+ }
+
+ }
+
+ PRINTK(" ---> FIFO ready\n");
+
+
+ outw(length, EL_BASE_ADDR + VX_W1_TX_PIO_WR_1);
+
+ /* Second dword meaningless */
+ outw(0x0, EL_BASE_ADDR + VX_W1_TX_PIO_WR_1);
+
+ print_packet((byte *)buf, length);
+ /* write packet */
+ {
+ unsigned int i, totdw;
+
+ totdw = ((length + 3) >> 1);
+ PRINTK("Buffer: (totdw = %d)\n", totdw);
+ for (i = 0; i < totdw; i++) {
+ outw( *(buf+i), EL_BASE_ADDR + VX_W1_TX_PIO_WR_1);
+ PRINTK("%04x ", *(buf+i));
+ if ( ((i % 8) == 0) && (i != 0) )
+ PRINTK("\n");
+ udelay(10);
+ }
+ PRINTK("\n\n");
+ }
+
+ /* wait for Tx complete */
+ PRINTK("Waiting for Tx to complete...\n");
+ while((inw(EL_BASE_ADDR + VX_STATUS) & S_COMMAND_IN_PROGRESS) != 0)
+ {
+ udelay(10);
+ }
+ PRINTK(" ---> Tx completed\n");
+
+ return length;
+}
+
+
+
+#endif /* CONFIG_DRIVER_3C589 */
--- /dev/null
+/*
+ * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer. 2. The name
+ * of the author may not be used to endorse or promote products derived from
+ * this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ October 2, 1994
+
+ Modified by: Andres Vega Garcia
+
+ INRIA - Sophia Antipolis, France
+ e-mail: avega@sophia.inria.fr
+ finger: avega@pax.inria.fr
+
+ */
+
+/*
+ * Created from if_epreg.h by Fred Gray (fgray@rice.edu) to support the
+ * 3c590 family.
+ */
+
+/*
+ * Modified by Shusuke Nisiyama <shu@athena.qe.eng.hokudai.ac.jp>
+ * for etherboot
+ * Mar. 14, 2000
+*/
+
+/*
+ * Ethernet software status per interface.
+ */
+
+/*
+ * Some global constants
+ */
+
+#define TX_INIT_RATE 16
+#define TX_INIT_MAX_RATE 64
+#define RX_INIT_LATENCY 64
+#define RX_INIT_EARLY_THRESH 64
+#define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */
+#define MIN_RX_EARLY_THRESHL 4
+
+#define EEPROMSIZE 0x40
+#define MAX_EEPROMBUSY 1000
+#define VX_LAST_TAG 0xd7
+#define VX_MAX_BOARDS 16
+#define VX_ID_PORT 0x100
+
+/*
+ * some macros to acces long named fields
+ */
+#define BASE (EL_BASE_ADDR)
+
+/*
+ * Commands to read/write EEPROM trough EEPROM command register (Window 0,
+ * Offset 0xa)
+ */
+#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */
+#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */
+#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
+#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */
+
+#define EEPROM_BUSY (1<<15)
+
+/*
+ * Some short functions, worth to let them be a macro
+ */
+
+/**************************************************************************
+ * *
+ * These define the EEPROM data structure. They are used in the probe
+ * function to verify the existence of the adapter after having sent
+ * the ID_Sequence.
+ *
+ * There are others but only the ones we use are defined here.
+ *
+ **************************************************************************/
+
+#define EEPROM_NODE_ADDR_0 0x0 /* Word */
+#define EEPROM_NODE_ADDR_1 0x1 /* Word */
+#define EEPROM_NODE_ADDR_2 0x2 /* Word */
+#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */
+#define EEPROM_MFG_ID 0x7 /* 0x6d50 */
+#define EEPROM_ADDR_CFG 0x8 /* Base addr */
+#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */
+#define EEPROM_OEM_ADDR_0 0xa /* Word */
+#define EEPROM_OEM_ADDR_1 0xb /* Word */
+#define EEPROM_OEM_ADDR_2 0xc /* Word */
+#define EEPROM_SOFT_INFO_2 0xf /* Software information 2 */
+
+#define NO_RX_OVN_ANOMALY (1<<5)
+
+/**************************************************************************
+ * *
+ * These are the registers for the 3Com 3c509 and their bit patterns when *
+ * applicable. They have been taken out the the "EtherLink III Parallel *
+ * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
+ * from 3com. *
+ * *
+ **************************************************************************/
+
+#define VX_COMMAND 0x0e /* Write. BASE+0x0e is always a
+ * command reg. */
+#define VX_STATUS 0x0e /* Read. BASE+0x0e is always status
+ * reg. */
+#define VX_WINDOW 0x0f /* Read. BASE+0x0f is always window
+ * reg. */
+/*
+ * Window 0 registers. Setup.
+ */
+/* Write */
+#define VX_W0_EEPROM_DATA 0x0c
+#define VX_W0_EEPROM_COMMAND 0x0a
+#define VX_W0_RESOURCE_CFG 0x08
+#define VX_W0_ADDRESS_CFG 0x06
+#define VX_W0_CONFIG_CTRL 0x04
+ /* Read */
+#define VX_W0_PRODUCT_ID 0x02
+#define VX_W0_MFG_ID 0x00
+
+
+/*
+ * Window 1 registers. Operating Set.
+ */
+/* Write */
+#define VX_W1_TX_PIO_WR_2 0x02
+#define VX_W1_TX_PIO_WR_1 0x00
+/* Read */
+#define VX_W1_FREE_TX 0x0c
+#define VX_W1_TX_STATUS 0x0b /* byte */
+#define VX_W1_TIMER 0x0a /* byte */
+#define VX_W1_RX_STATUS 0x08
+#define VX_W1_RX_PIO_RD_2 0x02
+#define VX_W1_RX_PIO_RD_1 0x00
+
+/*
+ * Window 2 registers. Station Address Setup/Read
+ */
+/* Read/Write */
+#define VX_W2_ADDR_5 0x05
+#define VX_W2_ADDR_4 0x04
+#define VX_W2_ADDR_3 0x03
+#define VX_W2_ADDR_2 0x02
+#define VX_W2_ADDR_1 0x01
+#define VX_W2_ADDR_0 0x00
+
+/*
+ * Window 3 registers. FIFO Management.
+ */
+/* Read */
+#define VX_W3_INTERNAL_CFG 0x00
+#define VX_W3_RESET_OPT 0x08
+#define VX_W3_FREE_TX 0x0c
+#define VX_W3_FREE_RX 0x0a
+
+/*
+ * Window 4 registers. Diagnostics.
+ */
+/* Read/Write */
+#define VX_W4_MEDIA_TYPE 0x0a
+#define VX_W4_CTRLR_STATUS 0x08
+#define VX_W4_NET_DIAG 0x06
+#define VX_W4_FIFO_DIAG 0x04
+#define VX_W4_HOST_DIAG 0x02
+#define VX_W4_TX_DIAG 0x00
+
+/*
+ * Window 5 Registers. Results and Internal status.
+ */
+/* Read */
+#define VX_W5_READ_0_MASK 0x0c
+#define VX_W5_INTR_MASK 0x0a
+#define VX_W5_RX_FILTER 0x08
+#define VX_W5_RX_EARLY_THRESH 0x06
+#define VX_W5_TX_AVAIL_THRESH 0x02
+#define VX_W5_TX_START_THRESH 0x00
+
+/*
+ * Window 6 registers. Statistics.
+ */
+/* Read/Write */
+#define TX_TOTAL_OK 0x0c
+#define RX_TOTAL_OK 0x0a
+#define TX_DEFERRALS 0x08
+#define RX_FRAMES_OK 0x07
+#define TX_FRAMES_OK 0x06
+#define RX_OVERRUNS 0x05
+#define TX_COLLISIONS 0x04
+#define TX_AFTER_1_COLLISION 0x03
+#define TX_AFTER_X_COLLISIONS 0x02
+#define TX_NO_SQE 0x01
+#define TX_CD_LOST 0x00
+
+/****************************************
+ *
+ * Register definitions.
+ *
+ ****************************************/
+
+/*
+ * Command register. All windows.
+ *
+ * 16 bit register.
+ * 15-11: 5-bit code for command to be executed.
+ * 10-0: 11-bit arg if any. For commands with no args;
+ * this can be set to anything.
+ */
+#define GLOBAL_RESET (unsigned short) 0x0000 /* Wait at least 1ms
+ * after issuing */
+#define WINDOW_SELECT (unsigned short) (0x1<<11)
+#define START_TRANSCEIVER (unsigned short) (0x2<<11) /* Read ADDR_CFG reg to
+ * determine whether
+ * this is needed. If
+ * so; wait 800 uSec
+ * before using trans-
+ * ceiver. */
+#define RX_DISABLE (unsigned short) (0x3<<11) /* state disabled on
+ * power-up */
+#define RX_ENABLE (unsigned short) (0x4<<11)
+#define RX_RESET (unsigned short) (0x5<<11)
+#define RX_DISCARD_TOP_PACK (unsigned short) (0x8<<11)
+#define TX_ENABLE (unsigned short) (0x9<<11)
+#define TX_DISABLE (unsigned short) (0xa<<11)
+#define TX_RESET (unsigned short) (0xb<<11)
+#define REQ_INTR (unsigned short) (0xc<<11)
+/*
+ * The following C_* acknowledge the various interrupts. Some of them don't
+ * do anything. See the manual.
+ */
+#define ACK_INTR (unsigned short) (0x6800)
+# define C_INTR_LATCH (unsigned short) (ACK_INTR|0x1)
+# define C_CARD_FAILURE (unsigned short) (ACK_INTR|0x2)
+# define C_TX_COMPLETE (unsigned short) (ACK_INTR|0x4)
+# define C_TX_AVAIL (unsigned short) (ACK_INTR|0x8)
+# define C_RX_COMPLETE (unsigned short) (ACK_INTR|0x10)
+# define C_RX_EARLY (unsigned short) (ACK_INTR|0x20)
+# define C_INT_RQD (unsigned short) (ACK_INTR|0x40)
+# define C_UPD_STATS (unsigned short) (ACK_INTR|0x80)
+#define SET_INTR_MASK (unsigned short) (0xe<<11)
+#define SET_RD_0_MASK (unsigned short) (0xf<<11)
+#define SET_RX_FILTER (unsigned short) (0x10<<11)
+# define FIL_INDIVIDUAL (unsigned short) (0x1)
+# define FIL_MULTICAST (unsigned short) (0x02)
+# define FIL_BRDCST (unsigned short) (0x04)
+# define FIL_PROMISC (unsigned short) (0x08)
+#define SET_RX_EARLY_THRESH (unsigned short) (0x11<<11)
+#define SET_TX_AVAIL_THRESH (unsigned short) (0x12<<11)
+#define SET_TX_START_THRESH (unsigned short) (0x13<<11)
+#define STATS_ENABLE (unsigned short) (0x15<<11)
+#define STATS_DISABLE (unsigned short) (0x16<<11)
+#define STOP_TRANSCEIVER (unsigned short) (0x17<<11)
+
+/*
+ * Status register. All windows.
+ *
+ * 15-13: Window number(0-7).
+ * 12: Command_in_progress.
+ * 11: reserved.
+ * 10: reserved.
+ * 9: reserved.
+ * 8: reserved.
+ * 7: Update Statistics.
+ * 6: Interrupt Requested.
+ * 5: RX Early.
+ * 4: RX Complete.
+ * 3: TX Available.
+ * 2: TX Complete.
+ * 1: Adapter Failure.
+ * 0: Interrupt Latch.
+ */
+#define S_INTR_LATCH (unsigned short) (0x1)
+#define S_CARD_FAILURE (unsigned short) (0x2)
+#define S_TX_COMPLETE (unsigned short) (0x4)
+#define S_TX_AVAIL (unsigned short) (0x8)
+#define S_RX_COMPLETE (unsigned short) (0x10)
+#define S_RX_EARLY (unsigned short) (0x20)
+#define S_INT_RQD (unsigned short) (0x40)
+#define S_UPD_STATS (unsigned short) (0x80)
+#define S_COMMAND_IN_PROGRESS (unsigned short) (0x1000)
+
+#define VX_BUSY_WAIT while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS)
+
+/* Address Config. Register.
+ * Window 0/Port 06
+ */
+
+#define ACF_CONNECTOR_BITS 14
+#define ACF_CONNECTOR_UTP 0
+#define ACF_CONNECTOR_AUI 1
+#define ACF_CONNECTOR_BNC 3
+
+#define INTERNAL_CONNECTOR_BITS 20
+#define INTERNAL_CONNECTOR_MASK 0x01700000
+
+/*
+ * FIFO Registers. RX Status.
+ *
+ * 15: Incomplete or FIFO empty.
+ * 14: 1: Error in RX Packet 0: Incomplete or no error.
+ * 13-11: Type of error.
+ * 1000 = Overrun.
+ * 1011 = Run Packet Error.
+ * 1100 = Alignment Error.
+ * 1101 = CRC Error.
+ * 1001 = Oversize Packet Error (>1514 bytes)
+ * 0010 = Dribble Bits.
+ * (all other error codes, no errors.)
+ *
+ * 10-0: RX Bytes (0-1514)
+ */
+#define ERR_INCOMPLETE (unsigned short) (0x8000)
+#define ERR_RX (unsigned short) (0x4000)
+#define ERR_MASK (unsigned short) (0x7800)
+#define ERR_OVERRUN (unsigned short) (0x4000)
+#define ERR_RUNT (unsigned short) (0x5800)
+#define ERR_ALIGNMENT (unsigned short) (0x6000)
+#define ERR_CRC (unsigned short) (0x6800)
+#define ERR_OVERSIZE (unsigned short) (0x4800)
+#define ERR_DRIBBLE (unsigned short) (0x1000)
+
+/*
+ * TX Status.
+ *
+ * Reports the transmit status of a completed transmission. Writing this
+ * register pops the transmit completion stack.
+ *
+ * Window 1/Port 0x0b.
+ *
+ * 7: Complete
+ * 6: Interrupt on successful transmission requested.
+ * 5: Jabber Error (TP Only, TX Reset required. )
+ * 4: Underrun (TX Reset required. )
+ * 3: Maximum Collisions.
+ * 2: TX Status Overflow.
+ * 1-0: Undefined.
+ *
+ */
+#define TXS_COMPLETE 0x80
+#define TXS_INTR_REQ 0x40
+#define TXS_JABBER 0x20
+#define TXS_UNDERRUN 0x10
+#define TXS_MAX_COLLISION 0x8
+#define TXS_STATUS_OVERFLOW 0x4
+
+#define RS_AUI (1<<5)
+#define RS_BNC (1<<4)
+#define RS_UTP (1<<3)
+#define RS_T4 (1<<0)
+#define RS_TX (1<<1)
+#define RS_FX (1<<2)
+#define RS_MII (1<<6)
+
+
+/*
+ * FIFO Status (Window 4)
+ *
+ * Supports FIFO diagnostics
+ *
+ * Window 4/Port 0x04.1
+ *
+ * 15: 1=RX receiving (RO). Set when a packet is being received
+ * into the RX FIFO.
+ * 14: Reserved
+ * 13: 1=RX underrun (RO). Generates Adapter Failure interrupt.
+ * Requires RX Reset or Global Reset command to recover.
+ * It is generated when you read past the end of a packet -
+ * reading past what has been received so far will give bad
+ * data.
+ * 12: 1=RX status overrun (RO). Set when there are already 8
+ * packets in the RX FIFO. While this bit is set, no additional
+ * packets are received. Requires no action on the part of
+ * the host. The condition is cleared once a packet has been
+ * read out of the RX FIFO.
+ * 11: 1=RX overrun (RO). Set when the RX FIFO is full (there
+ * may not be an overrun packet yet). While this bit is set,
+ * no additional packets will be received (some additional
+ * bytes can still be pending between the wire and the RX
+ * FIFO). Requires no action on the part of the host. The
+ * condition is cleared once a few bytes have been read out
+ * from the RX FIFO.
+ * 10: 1=TX overrun (RO). Generates adapter failure interrupt.
+ * Requires TX Reset or Global Reset command to recover.
+ * Disables Transmitter.
+ * 9-8: Unassigned.
+ * 7-0: Built in self test bits for the RX and TX FIFO's.
+ */
+#define FIFOS_RX_RECEIVING (unsigned short) 0x8000
+#define FIFOS_RX_UNDERRUN (unsigned short) 0x2000
+#define FIFOS_RX_STATUS_OVERRUN (unsigned short) 0x1000
+#define FIFOS_RX_OVERRUN (unsigned short) 0x0800
+#define FIFOS_TX_OVERRUN (unsigned short) 0x0400
+
+/*
+ * Misc defines for various things.
+ */
+#define TAG_ADAPTER 0xd0
+#define ACTIVATE_ADAPTER_TO_CONFIG 0xff
+#define ENABLE_DRQ_IRQ 0x0001
+#define MFG_ID 0x506d /* `TCM' */
+#define PROD_ID 0x5090
+#define GO_WINDOW(x) outw(WINDOW_SELECT|(x),BASE+VX_COMMAND)
+#define JABBER_GUARD_ENABLE 0x40
+#define LINKBEAT_ENABLE 0x80
+#define ENABLE_UTP (JABBER_GUARD_ENABLE | LINKBEAT_ENABLE)
+#define DISABLE_UTP 0x0
+#define RX_BYTES_MASK (unsigned short) (0x07ff)
+#define RX_ERROR 0x4000
+#define RX_INCOMPLETE 0x8000
+#define TX_INDICATE 1<<15
+#define is_eeprom_busy(b) (inw((b)+VX_W0_EEPROM_COMMAND)&EEPROM_BUSY)
+
+#define VX_IOSIZE 0x20
+
+#define VX_CONNECTORS 8
+
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
LIB = libdrivers.a
-OBJS = cs8900.o smc91111.o
+OBJS = cs8900.o smc91111.o 3c589.o
all: .depend $(START) $(LIB)
--- /dev/null
+/************************************************
+ * NAME : arm920t.h
+ * Version : 30 April 2002 *
+ *
+ * Based on 24x.h for the Samsung Development Board
+ ************************************************/
+
+#ifndef __ARM920T_H__
+#define __ARM920T_H__
+
+/* Memory control */
+#define rBWSCON (*(volatile unsigned *)0x14000000)
+#define rBANKCON0 (*(volatile unsigned *)0x14000004)
+#define rBANKCON1 (*(volatile unsigned *)0x14000008)
+#define rBANKCON2 (*(volatile unsigned *)0x1400000c)
+#define rBANKCON3 (*(volatile unsigned *)0x14000010)
+#define rBANKCON4 (*(volatile unsigned *)0x14000014)
+#define rBANKCON5 (*(volatile unsigned *)0x14000018)
+#define rBANKCON6 (*(volatile unsigned *)0x1400001c)
+#define rBANKCON7 (*(volatile unsigned *)0x14000020)
+#define rREFRESH (*(volatile unsigned *)0x14000024)
+#define rBANKSIZE (*(volatile unsigned *)0x14000028)
+#define rMRSRB6 (*(volatile unsigned *)0x1400002c)
+#define rMRSRB7 (*(volatile unsigned *)0x14000030)
+
+
+/* INTERRUPT */
+#define rSRCPND (*(volatile unsigned *)0x14400000)
+#define rINTMOD (*(volatile unsigned *)0x14400004)
+#define rINTMSK (*(volatile unsigned *)0x14400008)
+#define rPRIORITY (*(volatile unsigned *)0x1440000c)
+#define rINTPND (*(volatile unsigned *)0x14400010)
+#define rINTOFFSET (*(volatile unsigned *)0x14400014)
+
+
+/* DMA */
+#define rDISRC0 (*(volatile unsigned *)0x14600000)
+#define rDIDST0 (*(volatile unsigned *)0x14600004)
+#define rDCON0 (*(volatile unsigned *)0x14600008)
+#define rDSTAT0 (*(volatile unsigned *)0x1460000c)
+#define rDCSRC0 (*(volatile unsigned *)0x14600010)
+#define rDCDST0 (*(volatile unsigned *)0x14600014)
+#define rDMASKTRIG0 (*(volatile unsigned *)0x14600018)
+#define rDISRC1 (*(volatile unsigned *)0x14600020)
+#define rDIDST1 (*(volatile unsigned *)0x14600024)
+#define rDCON1 (*(volatile unsigned *)0x14600028)
+#define rDSTAT1 (*(volatile unsigned *)0x1460002c)
+#define rDCSRC1 (*(volatile unsigned *)0x14600030)
+#define rDCDST1 (*(volatile unsigned *)0x14600034)
+#define rDMASKTRIG1 (*(volatile unsigned *)0x14600038)
+#define rDISRC2 (*(volatile unsigned *)0x14600040)
+#define rDIDST2 (*(volatile unsigned *)0x14600044)
+#define rDCON2 (*(volatile unsigned *)0x14600048)
+#define rDSTAT2 (*(volatile unsigned *)0x1460004c)
+#define rDCSRC2 (*(volatile unsigned *)0x14600050)
+#define rDCDST2 (*(volatile unsigned *)0x14600054)
+#define rDMASKTRIG2 (*(volatile unsigned *)0x14600058)
+#define rDISRC3 (*(volatile unsigned *)0x14600060)
+#define rDIDST3 (*(volatile unsigned *)0x14600064)
+#define rDCON3 (*(volatile unsigned *)0x14600068)
+#define rDSTAT3 (*(volatile unsigned *)0x1460006c)
+#define rDCSRC3 (*(volatile unsigned *)0x14600070)
+#define rDCDST3 (*(volatile unsigned *)0x14600074)
+#define rDMASKTRIG3 (*(volatile unsigned *)0x14600078)
+
+
+/* CLOCK & POWER MANAGEMENT */
+#define rLOCKTIME (*(volatile unsigned *)0x14800000)
+#define rMPLLCON (*(volatile unsigned *)0x14800004)
+#define rUPLLCON (*(volatile unsigned *)0x14800008)
+#define rCLKCON (*(volatile unsigned *)0x1480000c)
+#define rCLKSLOW (*(volatile unsigned *)0x14800010)
+#define rCLKDIVN (*(volatile unsigned *)0x14800014)
+
+
+/* LCD CONTROLLER */
+#define rLCDCON1 (*(volatile unsigned *)0x14a00000)
+#define rLCDCON2 (*(volatile unsigned *)0x14a00004)
+#define rLCDCON3 (*(volatile unsigned *)0x14a00008)
+#define rLCDCON4 (*(volatile unsigned *)0x14a0000c)
+#define rLCDCON5 (*(volatile unsigned *)0x14a00010)
+#define rLCDSADDR1 (*(volatile unsigned *)0x14a00014)
+#define rLCDSADDR2 (*(volatile unsigned *)0x14a00018)
+#define rLCDSADDR3 (*(volatile unsigned *)0x14a0001c)
+#define rREDLUT (*(volatile unsigned *)0x14a00020)
+#define rGREENLUT (*(volatile unsigned *)0x14a00024)
+#define rBLUELUT (*(volatile unsigned *)0x14a00028)
+#define rDP1_2 (*(volatile unsigned *)0x14a0002c)
+#define rDP4_7 (*(volatile unsigned *)0x14a00030)
+#define rDP3_5 (*(volatile unsigned *)0x14a00034)
+#define rDP2_3 (*(volatile unsigned *)0x14a00038)
+#define rDP5_7 (*(volatile unsigned *)0x14a0003c)
+#define rDP3_4 (*(volatile unsigned *)0x14a00040)
+#define rDP4_5 (*(volatile unsigned *)0x14a00044)
+#define rDP6_7 (*(volatile unsigned *)0x14a00048)
+#define rDITHMODE (*(volatile unsigned *)0x14a0004c)
+#define rTPAL (*(volatile unsigned *)0x14a00050)
+#define PALETTE (0x14a00400)//SJS
+
+
+/* UART */
+#define rULCON0 (*(volatile unsigned char *)0x15000000)
+#define rUCON0 (*(volatile unsigned short *)0x15000004)
+#define rUFCON0 (*(volatile unsigned char *)0x15000008)
+#define rUMCON0 (*(volatile unsigned char *)0x1500000c)
+#define rUTRSTAT0 (*(volatile unsigned char *)0x15000010)
+#define rUERSTAT0 (*(volatile unsigned char *)0x15000014)
+#define rUFSTAT0 (*(volatile unsigned short *)0x15000018)
+#define rUMSTAT0 (*(volatile unsigned char *)0x1500001c)
+#define rUBRDIV0 (*(volatile unsigned short *)0x15000028)
+
+#define rULCON1 (*(volatile unsigned char *)0x15004000)
+#define rUCON1 (*(volatile unsigned short *)0x15004004)
+#define rUFCON1 (*(volatile unsigned char *)0x15004008)
+#define rUMCON1 (*(volatile unsigned char *)0x1500400c)
+#define rUTRSTAT1 (*(volatile unsigned char *)0x15004010)
+#define rUERSTAT1 (*(volatile unsigned char *)0x15004014)
+#define rUFSTAT1 (*(volatile unsigned short *)0x15004018)
+#define rUMSTAT1 (*(volatile unsigned char *)0x1500401c)
+#define rUBRDIV1 (*(volatile unsigned short *)0x15004028)
+
+#ifdef __BIG_ENDIAN
+#define rUTXH0 (*(volatile unsigned char *)0x15000023)
+#define rURXH0 (*(volatile unsigned char *)0x15000027)
+#define rUTXH1 (*(volatile unsigned char *)0x15004023)
+#define rURXH1 (*(volatile unsigned char *)0x15004027)
+
+#define WrUTXH0(ch) (*(volatile unsigned char *)0x15000023)=(unsigned char)(ch)
+#define RdURXH0() (*(volatile unsigned char *)0x15000027)
+#define WrUTXH1(ch) (*(volatile unsigned char *)0x15004023)=(unsigned char)(ch)
+#define RdURXH1() (*(volatile unsigned char *)0x15004027)
+
+#define UTXH0 (0x15000020+3) //byte_access address by DMA
+#define URXH0 (0x15000024+3)
+#define UTXH1 (0x15004020+3)
+#define URXH1 (0x15004024+3)
+
+#else //Little Endian
+#define rUTXH0 (*(volatile unsigned char *)0x15000020)
+#define rURXH0 (*(volatile unsigned char *)0x15000024)
+#define rUTXH1 (*(volatile unsigned char *)0x15004020)
+#define rURXH1 (*(volatile unsigned char *)0x15004024)
+
+#define WrUTXH0(ch) (*(volatile unsigned char *)0x15000020)=(unsigned char)(ch)
+#define RdURXH0() (*(volatile unsigned char *)0x15000024)
+#define WrUTXH1(ch) (*(volatile unsigned char *)0x15004020)=(unsigned char)(ch)
+#define RdURXH1() (*(volatile unsigned char *)0x15004024)
+
+#define UTXH0 (0x15000020) //byte_access address by DMA
+#define URXH0 (0x15000024)
+#define UTXH1 (0x15004020)
+#define URXH1 (0x15004024)
+#endif
+
+
+/* PWM TIMER */
+#define rTCFG0 (*(volatile unsigned *)0x15100000)
+#define rTCFG1 (*(volatile unsigned *)0x15100004)
+#define rTCON (*(volatile unsigned *)0x15100008)
+#define rTCNTB0 (*(volatile unsigned *)0x1510000c)
+#define rTCMPB0 (*(volatile unsigned *)0x15100010)
+#define rTCNTO0 (*(volatile unsigned *)0x15100014)
+#define rTCNTB1 (*(volatile unsigned *)0x15100018)
+#define rTCMPB1 (*(volatile unsigned *)0x1510001c)
+#define rTCNTO1 (*(volatile unsigned *)0x15100020)
+#define rTCNTB2 (*(volatile unsigned *)0x15100024)
+#define rTCMPB2 (*(volatile unsigned *)0x15100028)
+#define rTCNTO2 (*(volatile unsigned *)0x1510002c)
+#define rTCNTB3 (*(volatile unsigned *)0x15100030)
+#define rTCMPB3 (*(volatile unsigned *)0x15100034)
+#define rTCNTO3 (*(volatile unsigned *)0x15100038)
+#define rTCNTB4 (*(volatile unsigned *)0x1510003c)
+#define rTCNTO4 (*(volatile unsigned *)0x15100040)
+
+
+/* USB DEVICE */
+#define rFUNC_ADDR_REG (*(volatile unsigned *)0x15200140)
+#define rPWR_REG (*(volatile unsigned *)0x15200144)
+#define rINT_REG (*(volatile unsigned *)0x15200148)
+#define rINT_MASK_REG (*(volatile unsigned *)0x1520014c)
+#define rFRAME_NUM_REG (*(volatile unsigned *)0x15200150)
+#define rRESUME_CON_REG (*(volatile unsigned *)0x15200154)
+#define rEP0_CSR (*(volatile unsigned *)0x15200160)
+#define rEP0_MAXP (*(volatile unsigned *)0x15200164)
+#define rEP0_OUT_CNT (*(volatile unsigned *)0x15200168)
+#define rEP0_FIFO (*(volatile unsigned *)0x1520016c)
+#define rEP1_IN_CSR (*(volatile unsigned *)0x15200180)
+#define rEP1_IN_MAXP (*(volatile unsigned *)0x15200184)
+#define rEP1_FIFO (*(volatile unsigned *)0x15200188)
+#define rEP2_IN_CSR (*(volatile unsigned *)0x15200190)
+#define rEP2_IN_MAXP (*(volatile unsigned *)0x15200194)
+#define rEP2_FIFO (*(volatile unsigned *)0x15200198)
+#define rEP3_OUT_CSR (*(volatile unsigned *)0x152001a0)
+#define rEP3_OUT_MAXP (*(volatile unsigned *)0x152001a4)
+#define rEP3_OUT_CNT (*(volatile unsigned *)0x152001a8)
+#define rEP3_FIFO (*(volatile unsigned *)0x152001ac)
+#define rEP4_OUT_CSR (*(volatile unsigned *)0x152001b0)
+#define rEP4_OUT_MAXP (*(volatile unsigned *)0x152001b4)
+#define rEP4_OUT_CNT (*(volatile unsigned *)0x152001b8)
+#define rEP4_FIFO (*(volatile unsigned *)0x152001bc)
+#define rDMA_CON (*(volatile unsigned *)0x152001c0)
+#define rDMA_UNIT (*(volatile unsigned *)0x152001c4)
+#define rDMA_FIFO (*(volatile unsigned *)0x152001c8)
+#define rDMA_TX (*(volatile unsigned *)0x152001cc)
+#define rTEST_MODE (*(volatile unsigned *)0x152001f4)
+#define rIN_CON_REG (*(volatile unsigned *)0x152001f8)
+
+
+/* WATCH DOG TIMER */
+#define rWTCON (*(volatile unsigned *)0x15300000)
+#define rWTDAT (*(volatile unsigned *)0x15300004)
+#define rWTCNT (*(volatile unsigned *)0x15300008)
+
+
+/* IIC */
+#define rIICCON (*(volatile unsigned *)0x15400000)
+#define rIICSTAT (*(volatile unsigned *)0x15400004)
+#define rIICADD (*(volatile unsigned *)0x15400008)
+#define rIICDS (*(volatile unsigned *)0x1540000c)
+
+
+/* IIS */
+#define rIISCON (*(volatile unsigned *)0x15508000)
+#define rIISMOD (*(volatile unsigned *)0x15508004)
+#define rIISPSR (*(volatile unsigned *)0x15508008)
+#define rIISFIFCON (*(volatile unsigned *)0x1550800c)
+
+#ifdef __BIG_ENDIAN
+#define IISFIF ((volatile unsigned short *)0x15508012)
+
+#else //Little Endian
+#define IISFIF ((volatile unsigned short *)0x15508010)
+#endif
+
+
+/* I/O PORT */
+#define rPACON (*(volatile unsigned *)0x15600000)
+#define rPADAT (*(volatile unsigned *)0x15600004)
+
+#define rPBCON (*(volatile unsigned *)0x15600008)
+#define rPBDAT (*(volatile unsigned *)0x1560000c)
+#define rPBUP (*(volatile unsigned *)0x15600010)
+
+#define rPCCON (*(volatile unsigned *)0x15600014)
+#define rPCDAT (*(volatile unsigned *)0x15600018)
+#define rPCUP (*(volatile unsigned *)0x1560001c)
+
+#define rPDCON (*(volatile unsigned *)0x15600020)
+#define rPDDAT (*(volatile unsigned *)0x15600024)
+#define rPDUP (*(volatile unsigned *)0x15600028)
+
+#define rPECON (*(volatile unsigned *)0x1560002c)
+#define rPEDAT (*(volatile unsigned *)0x15600030)
+#define rPEUP (*(volatile unsigned *)0x15600034)
+
+#define rPFCON (*(volatile unsigned *)0x15600038)
+#define rPFDAT (*(volatile unsigned *)0x1560003c)
+#define rPFUP (*(volatile unsigned *)0x15600040)
+
+#define rPGCON (*(volatile unsigned *)0x15600044)
+#define rPGDAT (*(volatile unsigned *)0x15600048)
+#define rPGUP (*(volatile unsigned *)0x1560004c)
+
+#define rOPENCR (*(volatile unsigned *)0x15600050)
+#define rMISCCR (*(volatile unsigned *)0x15600054)
+#define rEXTINT (*(volatile unsigned *)0x15600058)
+
+
+/* RTC */
+#ifdef __BIG_ENDIAN
+#define rRTCCON (*(volatile unsigned char *)0x15700043)
+#define rRTCALM (*(volatile unsigned char *)0x15700053)
+#define rALMSEC (*(volatile unsigned char *)0x15700057)
+#define rALMMIN (*(volatile unsigned char *)0x1570005b)
+#define rALMHOUR (*(volatile unsigned char *)0x1570005f)
+#define rALMDAY (*(volatile unsigned char *)0x15700063)
+#define rALMMON (*(volatile unsigned char *)0x15700067)
+#define rALMYEAR (*(volatile unsigned char *)0x1570006b)
+#define rRTCRST (*(volatile unsigned char *)0x1570006f)
+#define rBCDSEC (*(volatile unsigned char *)0x15700073)
+#define rBCDMIN (*(volatile unsigned char *)0x15700077)
+#define rBCDHOUR (*(volatile unsigned char *)0x1570007b)
+#define rBCDDAY (*(volatile unsigned char *)0x1570007f)
+#define rBCDDATE (*(volatile unsigned char *)0x15700083)
+#define rBCDMON (*(volatile unsigned char *)0x15700087)
+#define rBCDYEAR (*(volatile unsigned char *)0x1570008b)
+#define rTICINT (*(volatile unsigned char *)0x15700047)
+
+#else //Little Endian
+#define rRTCCON (*(volatile unsigned char *)0x15700040)
+#define rRTCALM (*(volatile unsigned char *)0x15700050)
+#define rALMSEC (*(volatile unsigned char *)0x15700054)
+#define rALMMIN (*(volatile unsigned char *)0x15700058)
+#define rALMHOUR (*(volatile unsigned char *)0x1570005c)
+#define rALMDAY (*(volatile unsigned char *)0x15700060)
+#define rALMMON (*(volatile unsigned char *)0x15700064)
+#define rALMYEAR (*(volatile unsigned char *)0x15700068)
+#define rRTCRST (*(volatile unsigned char *)0x1570006c)
+#define rBCDSEC (*(volatile unsigned char *)0x15700070)
+#define rBCDMIN (*(volatile unsigned char *)0x15700074)
+#define rBCDHOUR (*(volatile unsigned char *)0x15700078)
+#define rBCDDAY (*(volatile unsigned char *)0x1570007c)
+#define rBCDDATE (*(volatile unsigned char *)0x15700080)
+#define rBCDMON (*(volatile unsigned char *)0x15700084)
+#define rBCDYEAR (*(volatile unsigned char *)0x15700088)
+#define rTICINT (*(volatile unsigned char *)0x15700044)
+#endif
+
+
+/* ADC */
+#define rADCCON (*(volatile unsigned *)0x15800000)
+#define rADCDAT (*(volatile unsigned *)0x15800004)
+
+
+/* SPI */
+#define rSPCON (*(volatile unsigned *)0x15900000)
+#define rSPSTA (*(volatile unsigned *)0x15900004)
+#define rSPPIN (*(volatile unsigned *)0x15900008)
+#define rSPPRE (*(volatile unsigned *)0x1590000c)
+#define rSPTDAT (*(volatile unsigned *)0x15900010)
+#define rSPRDAT (*(volatile unsigned *)0x15900014)
+
+
+/* MMC INTERFACE */
+#define rMMCON (*(volatile unsigned *)0x15a00000)
+#define rMMCRR (*(volatile unsigned *)0x15a00004)
+#define rMMFCON (*(volatile unsigned *)0x15a00008)
+#define rMMSTA (*(volatile unsigned *)0x15a0000c)
+#define rMMFSTA (*(volatile unsigned *)0x15a00010)
+#define rMMPRE (*(volatile unsigned *)0x15a00014)
+#define rMMLEN (*(volatile unsigned *)0x15a00018)
+#define rMMCR7 (*(volatile unsigned *)0x15a0001c)
+#define rMMRSP0 (*(volatile unsigned *)0x15a00020)
+#define rMMRSP1 (*(volatile unsigned *)0x15a00024)
+#define rMMRSP2 (*(volatile unsigned *)0x15a00028)
+#define rMMRSP3 (*(volatile unsigned *)0x15a0002c)
+#define rMMCMD0 (*(volatile unsigned *)0x15a00030)
+#define rMMCMD1 (*(volatile unsigned *)0x15a00034)
+#define rMMCR16 (*(volatile unsigned *)0x15a00038)
+#define rMMDAT (*(volatile unsigned *)0x15a0003c)
+
+
+
+/* ISR */
+#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0))
+#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4))
+#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8))
+#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xc))
+#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10))
+#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14))
+#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18))
+#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1c))
+
+#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20))
+#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24))
+#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28))
+#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2c))
+#define pISR_EINT4 (*(unsigned *)(_ISR_STARTADDRESS+0x30))
+#define pISR_EINT5 (*(unsigned *)(_ISR_STARTADDRESS+0x34))
+#define pISR_EINT6 (*(unsigned *)(_ISR_STARTADDRESS+0x38))
+#define pISR_EINT7 (*(unsigned *)(_ISR_STARTADDRESS+0x3c))
+#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40))
+#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44))
+#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48))
+#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4c))
+#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50))
+#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54))
+#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58))
+#define pISR_UERR01 (*(unsigned *)(_ISR_STARTADDRESS+0x5c))
+#define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60))
+#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64))
+#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68))
+#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6c))
+#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70))
+#define pISR_MMC (*(unsigned *)(_ISR_STARTADDRESS+0x74))
+#define pISR_SPI (*(unsigned *)(_ISR_STARTADDRESS+0x78))
+#define pISR_URXD0 (*(unsigned *)(_ISR_STARTADDRESS+0x7c))
+#define pISR_URXD1 (*(unsigned *)(_ISR_STARTADDRESS+0x80))
+#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84))
+#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88))
+#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8c))
+#define pISR_UTXD0 (*(unsigned *)(_ISR_STARTADDRESS+0x90))
+#define pISR_UTXD1 (*(unsigned *)(_ISR_STARTADDRESS+0x94))
+#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98))
+#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xa0))
+
+
+/* PENDING BIT */
+#define BIT_EINT0 (0x1)
+#define BIT_EINT1 (0x1<<1)
+#define BIT_EINT2 (0x1<<2)
+#define BIT_EINT3 (0x1<<3)
+#define BIT_EINT4 (0x1<<4)
+#define BIT_EINT5 (0x1<<5)
+#define BIT_EINT6 (0x1<<6)
+#define BIT_EINT7 (0x1<<7)
+#define BIT_TICK (0x1<<8)
+#define BIT_WDT (0x1<<9)
+#define BIT_TIMER0 (0x1<<10)
+#define BIT_TIMER1 (0x1<<11)
+#define BIT_TIMER2 (0x1<<12)
+#define BIT_TIMER3 (0x1<<13)
+#define BIT_TIMER4 (0x1<<14)
+#define BIT_UERR01 (0x1<<15)
+#define BIT_NOTUSED (0x1<<16)
+#define BIT_DMA0 (0x1<<17)
+#define BIT_DMA1 (0x1<<18)
+#define BIT_DMA2 (0x1<<19)
+#define BIT_DMA3 (0x1<<20)
+#define BIT_MMC (0x1<<21)
+#define BIT_SPI (0x1<<22)
+#define BIT_URXD0 (0x1<<23)
+#define BIT_URXD1 (0x1<<24)
+#define BIT_USBD (0x1<<25)
+#define BIT_USBH (0x1<<26)
+#define BIT_IIC (0x1<<27)
+#define BIT_UTXD0 (0x1<<28)
+#define BIT_UTXD1 (0x1<<29)
+#define BIT_RTC (0x1<<30)
+#define BIT_ADC (0x1<<31)
+#define BIT_ALLMSK (0xffffffff)
+
+#define ClearPending(bit) {\
+ rSRCPND = bit;\
+ rINTPND = bit;\
+ rINTPND;\
+ }
+//Wait until rINTPND is changed for the case that the ISR is very short.
+#endif /*__ARM920T_H__*/
+
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <gj@denx.de>
+ *
+ * Configuation settings for the SAMSUNG board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#define CONFIG_INIT_CRITICAL /* undef for developing */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM920T 1 /* This is an arm920t CPU */
+#define CONFIG_SAMSUNG 1 /* on an SAMSUNG Board */
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
+#define CS8900_BASE 0x07000300 /* agrees with WIN CE PA */
+#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SAMSUNG */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+#ifndef USE_920T_MMU
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_CACHE)
+#else
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY 3
+//#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600"
+//#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 134.98.93.36
+#define CONFIG_SERVERIP 134.98.93.22
+//#define CONFIG_BOOTFILE "elinos-lart"
+//#define CONFIG_BOOTCOMMAND "tftp; bootm"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+/* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "SAMSUNG # " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0c000000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0e000000 /* 32 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0x0cf00000 /* default load address */
+
+/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
+/* it to wrap 100 times (total 1562500) to get 1 sec. */
+#define CFG_HZ 1562500
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#ifndef __ASSEMBLY__
+/*-----------------------------------------------------------------------
+ * Board specific extension for bd_info
+ *
+ * This structure is embedded in the global bd_info (bd_t) structure
+ * and can be used by the board specific code (eg board/...)
+ */
+
+struct bd_info_ext
+{
+ /* helper variable for board environment handling
+ *
+ * env_crc_valid == 0 => uninitialised
+ * env_crc_valid > 0 => environment crc in flash is valid
+ * env_crc_valid < 0 => environment crc in flash is invalid
+ */
+ int env_crc_valid;
+};
+#endif
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x0c000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
+
+#define CFG_FLASH_BASE PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT (64) /* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C0000) /* Addr of Environment Sector */
+#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
+
+#endif /* __CONFIG_H */
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_CS8900 0 /* we DO NOT have a CS8900 on-board */
-#define CS8900_BASE 0x20008300
-#define CS8900_BUS16 1
+#define CONFIG_DRIVER_3C589 1
/*
* select serial console configuration
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200"
-#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
#define CONFIG_NETMASK 255.255.0.0
-#define CONFIG_IPADDR 172.22.2.131
-#define CONFIG_SERVERIP 172.22.2.126
-#define CONFIG_BOOTFILE "elinos-shannon"
#define CONFIG_BOOTCOMMAND "help"
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
projects / users / rw / armboot.git / commitdiff