/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
 #define IRQ_CLEAR                              BIT(0)
 
-/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
-#define RCVR_DETECT                            BIT(0)
-
 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
 #define CLAMP_EN                               BIT(0) /* enables i/o clamp_n */
 
        QPHY_PCS_STATUS,
        QPHY_PCS_AUTONOMOUS_MODE_CTRL,
        QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
-       QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
        QPHY_PCS_POWER_DOWN_CONTROL,
        /* Keep last to ensure regs_layout arrays are properly initialized */
        QPHY_LAYOUT_SIZE
        [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x04,
        [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
        [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
-       [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
 };
 
 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {