]> www.infradead.org Git - users/jedix/linux-maple.git/commitdiff
drm/amdgpu/mes: add mes mapping legacy queue switch
authorJack Xiao <Jack.Xiao@amd.com>
Thu, 22 Aug 2024 10:18:51 +0000 (18:18 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 2 Sep 2024 17:05:39 +0000 (13:05 -0400)
For mes11 old firmware has issue to map legacy queue,
add a flag to switch mes to map legacy queue.

Fixes: f9d8c5c7855d ("drm/amdgpu/gfx: enable mes to map legacy queue support")
Reported-by: Andrew Worsley <amworsley@gmail.com>
Link: https://lists.freedesktop.org/archives/amd-gfx/2024-August/112773.html
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 52491d97aadcde543986d596ed55f70bf2142851)

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

index c770cb201e64bc82a7337eb57437b744d02f4ea3..1849510a308add343a4e1d3e8ef32fa442e034af 100644 (file)
@@ -657,7 +657,7 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id)
        uint64_t queue_mask = 0;
        int r, i, j;
 
-       if (adev->enable_mes)
+       if (adev->mes.enable_legacy_queue_map)
                return amdgpu_gfx_mes_enable_kcq(adev, xcc_id);
 
        if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources)
@@ -719,7 +719,7 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id)
 
        amdgpu_device_flush_hdp(adev, NULL);
 
-       if (adev->enable_mes) {
+       if (adev->mes.enable_legacy_queue_map) {
                for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
                        j = i + xcc_id * adev->gfx.num_gfx_rings;
                        r = amdgpu_mes_map_legacy_queue(adev,
index 0bc837dab578f96798787a535ec75446496a6ff4..bcce1add4ef68d863497d55a1b246eb14e1e6bff 100644 (file)
@@ -75,6 +75,7 @@ struct amdgpu_mes {
 
        uint32_t                        sched_version;
        uint32_t                        kiq_version;
+       bool                            enable_legacy_queue_map;
 
        uint32_t                        total_max_queue;
        uint32_t                        max_doorbell_slices;
index 2ea8223eb969aeb8a58affc8711875cfa48ad53d..8aded0a67037b40ba143f2eaf89560cdecb6e8ef 100644 (file)
@@ -693,6 +693,28 @@ static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev,
                              (void **)&adev->mes.ucode_fw_ptr[pipe]);
 }
 
+static void mes_v11_0_get_fw_version(struct amdgpu_device *adev)
+{
+       int pipe;
+
+       /* get MES scheduler/KIQ versions */
+       mutex_lock(&adev->srbm_mutex);
+
+       for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
+               soc21_grbm_select(adev, 3, pipe, 0, 0);
+
+               if (pipe == AMDGPU_MES_SCHED_PIPE)
+                       adev->mes.sched_version =
+                               RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
+               else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
+                       adev->mes.kiq_version =
+                               RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
+       }
+
+       soc21_grbm_select(adev, 0, 0, 0, 0);
+       mutex_unlock(&adev->srbm_mutex);
+}
+
 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)
 {
        uint64_t ucode_addr;
@@ -1062,18 +1084,6 @@ static int mes_v11_0_queue_init(struct amdgpu_device *adev,
                mes_v11_0_queue_init_register(ring);
        }
 
-       /* get MES scheduler/KIQ versions */
-       mutex_lock(&adev->srbm_mutex);
-       soc21_grbm_select(adev, 3, pipe, 0, 0);
-
-       if (pipe == AMDGPU_MES_SCHED_PIPE)
-               adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
-       else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
-               adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
-
-       soc21_grbm_select(adev, 0, 0, 0, 0);
-       mutex_unlock(&adev->srbm_mutex);
-
        return 0;
 }
 
@@ -1320,15 +1330,24 @@ static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)
 
        mes_v11_0_enable(adev, true);
 
+       mes_v11_0_get_fw_version(adev);
+
        mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring);
 
        r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);
        if (r)
                goto failure;
 
-       r = mes_v11_0_hw_init(adev);
-       if (r)
-               goto failure;
+       if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47)
+               adev->mes.enable_legacy_queue_map = true;
+       else
+               adev->mes.enable_legacy_queue_map = false;
+
+       if (adev->mes.enable_legacy_queue_map) {
+               r = mes_v11_0_hw_init(adev);
+               if (r)
+                       goto failure;
+       }
 
        return r;
 
index e39a58d262c94e2392bd25922cd0a8866e9d51a4..a79a8adc3aa5b1307fe259e995a444db42d91889 100644 (file)
@@ -1266,6 +1266,7 @@ static int mes_v12_0_sw_init(void *handle)
        adev->mes.funcs = &mes_v12_0_funcs;
        adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init;
        adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini;
+       adev->mes.enable_legacy_queue_map = true;
 
        adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE;
 
@@ -1422,9 +1423,11 @@ static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev)
                mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_KIQ_PIPE);
        }
 
-       r = mes_v12_0_hw_init(adev);
-       if (r)
-               goto failure;
+       if (adev->mes.enable_legacy_queue_map) {
+               r = mes_v12_0_hw_init(adev);
+               if (r)
+                       goto failure;
+       }
 
        return r;