drm/i915/skl: Stage the pipe DDB allocation

To correctly flush the new DDB allocation we need to know about the pipe
allocation layout inside the DDB in order to sequence the re-allocation
to not cause a newly allocated pipe to fetch from a space that was
previously allocated to another pipe.

This patch preserves the per-pipe (start,end) allocation to be used in
the flush.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cf84b6d30eaef2157c7147cf15987f518db206a5..01d741d37a8536ebadedb7015731dffbc8e268b5 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1406,6 +1406,7 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
 }
 
 struct skl_ddb_allocation {
+       struct skl_ddb_entry pipe[I915_MAX_PIPES];
        struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
        struct skl_ddb_entry cursor[I915_MAX_PIPES];
 };

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7fdccba93385504bd8c56eef265b994ffdbfb0a8..cd2b3351ff45941e0196fe9579d62b136d6e5ce1 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3119,13 +3119,13 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
        struct drm_device *dev = crtc->dev;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        enum pipe pipe = intel_crtc->pipe;
-       struct skl_ddb_entry alloc;
+       struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
        uint16_t alloc_size, start, cursor_blocks;
        unsigned int total_data_rate;
        int plane;
 
-       skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, &alloc);
-       alloc_size = skl_ddb_entry_size(&alloc);
+       skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
+       alloc_size = skl_ddb_entry_size(alloc);
        if (alloc_size == 0) {
                memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
                memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
@@ -3133,11 +3133,11 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
        }
 
        cursor_blocks = skl_cursor_allocation(config);
-       ddb->cursor[pipe].start = alloc.end - cursor_blocks;
-       ddb->cursor[pipe].end = alloc.end;
+       ddb->cursor[pipe].start = alloc->end - cursor_blocks;
+       ddb->cursor[pipe].end = alloc->end;
 
        alloc_size -= cursor_blocks;
-       alloc.end -= cursor_blocks;
+       alloc->end -= cursor_blocks;
 
        /*
         * Each active plane get a portion of the remaining space, in
@@ -3147,7 +3147,7 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
         */
        total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
 
-       start = alloc.start;
+       start = alloc->start;
        for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
                const struct intel_plane_wm_parameters *p;
                unsigned int data_rate;