return num_tc - 1;
 }
 
+int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out)
+{
+       u32 in[MLX5_ST_SZ_DW(dcbx_param)] = {0};
+
+       MLX5_SET(dcbx_param, in, port_number, 1);
+
+       return  mlx5_core_access_reg(mdev, in, sizeof(in), out,
+                                   sizeof(in), MLX5_REG_DCBX_PARAM, 0, 0);
+}
+
+int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in)
+{
+       u32 out[MLX5_ST_SZ_DW(dcbx_param)];
+
+       MLX5_SET(dcbx_param, in, port_number, 1);
+
+       return mlx5_core_access_reg(mdev, in, sizeof(out), out,
+                                   sizeof(out), MLX5_REG_DCBX_PARAM, 0, 1);
+}
+
 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc)
 {
        u32 in[MLX5_ST_SZ_DW(qtct_reg)] = {0};
 
 enum {
        MLX5_REG_QETCR           = 0x4005,
        MLX5_REG_QTCT            = 0x400a,
+       MLX5_REG_DCBX_PARAM      = 0x4020,
+       MLX5_REG_DCBX_APP        = 0x4021,
        MLX5_REG_PCAP            = 0x5001,
        MLX5_REG_PMTU            = 0x5003,
        MLX5_REG_PTYS            = 0x5004,
        MLX5_REG_MPCNT           = 0x9051,
 };
 
+enum mlx5_dcbx_oper_mode {
+       MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
+       MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
+};
+
 enum {
        MLX5_ATOMIC_OPS_CMP_SWAP        = 1 << 0,
        MLX5_ATOMIC_OPS_FETCH_ADD       = 1 << 1,
 
 int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
                             u16 offset, u16 size, u8 *data);
 
+int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out);
+int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in);
 #endif /* __MLX5_PORT_H__ */