#define CS35L56_DSP1_XMEM_UNPACKED24_0                 0x2800000
 #define CS35L56_DSP1_FW_VER                            0x2800010
 #define CS35L56_DSP1_HALO_STATE                                0x28021E0
+#define CS35L56_B2_DSP1_HALO_STATE                     0x2803D20
 #define CS35L56_DSP1_PM_CUR_STATE                      0x2804308
+#define CS35L56_B2_DSP1_PM_CUR_STATE                   0x2804678
 #define CS35L56_DSP1_XMEM_UNPACKED24_8191              0x2807FFC
 #define CS35L56_DSP1_CORE_BASE                         0x2B80000
 #define CS35L56_DSP1_SCRATCH1                          0x2B805C0
 
        .posture_number = CS35L56_MAIN_POSTURE_NUMBER,
 };
 
+static const struct cs35l56_fw_reg cs35l56_b2_fw_reg = {
+       .fw_ver = CS35L56_DSP1_FW_VER,
+       .halo_state = CS35L56_B2_DSP1_HALO_STATE,
+       .pm_cur_stat = CS35L56_B2_DSP1_PM_CUR_STATE,
+       .prot_sts = CS35L56_PROTECTION_STATUS,
+       .transducer_actual_ps = CS35L56_TRANSDUCER_ACTUAL_PS,
+       .user_mute = CS35L56_MAIN_RENDER_USER_MUTE,
+       .user_volume = CS35L56_MAIN_RENDER_USER_VOLUME,
+       .posture_number = CS35L56_MAIN_POSTURE_NUMBER,
+};
+
 static const struct cs35l56_fw_reg cs35l63_fw_reg = {
        .fw_ver = CS35L63_DSP1_FW_VER,
        .halo_state = CS35L63_DSP1_HALO_STATE,
 {
        switch (cs35l56_base->type) {
        default:
-               cs35l56_base->fw_reg = &cs35l56_fw_reg;
+               switch (cs35l56_base->rev) {
+               case 0xb0:
+                       cs35l56_base->fw_reg = &cs35l56_fw_reg;
+                       break;
+               default:
+                       cs35l56_base->fw_reg = &cs35l56_b2_fw_reg;
+                       break;
+               }
                break;
        case 0x63:
                cs35l56_base->fw_reg = &cs35l63_fw_reg;
        REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET),
 };
 
+static const struct reg_sequence cs35l56_b2_system_reset_seq[] = {
+       REG_SEQ0(CS35L56_B2_DSP1_HALO_STATE, 0),
+       REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET),
+};
+
 static const struct reg_sequence cs35l63_system_reset_seq[] = {
        REG_SEQ0(CS35L63_DSP1_HALO_STATE, 0),
        REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET),
        case 0x54:
        case 0x56:
        case 0x57:
-               regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
-                                               cs35l56_system_reset_seq,
-                                               ARRAY_SIZE(cs35l56_system_reset_seq));
+               switch (cs35l56_base->rev) {
+               case 0xb0:
+                       regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
+                                                       cs35l56_system_reset_seq,
+                                                       ARRAY_SIZE(cs35l56_system_reset_seq));
+                       break;
+               default:
+                       regmap_multi_reg_write_bypassed(cs35l56_base->regmap,
+                                                       cs35l56_b2_system_reset_seq,
+                                                       ARRAY_SIZE(cs35l56_b2_system_reset_seq));
+                       break;
+               }
                break;
        case 0x63:
                regmap_multi_reg_write_bypassed(cs35l56_base->regmap,