drm/i915: Implement workaround for CDCLK PLL disable/enable

It was reported that we might get a hung and loss of register access in
some cases when CDCLK PLL is disabled and then enabled, while squashing
is enabled.
As a workaround it was proposed by HW team that SW should disable squashing
when CDCLK PLL is being reenabled.

v2: - Added WA number comment(Rodrigo Vivi)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230130135836.12738-1-stanislav.lisovskiy@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 7e16b655c83380186b6720622839bbd41555768a..82da76b586edbada87d32b1514cf33d5e7b1803d 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1801,6 +1801,13 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
        return true;
 }
 
+static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
+{
+       return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) &&
+               dev_priv->display.cdclk.hw.vco > 0 &&
+               HAS_CDCLK_SQUASH(dev_priv));
+}
+
 static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
                           const struct intel_cdclk_config *cdclk_config,
                           enum pipe pipe)
@@ -1815,9 +1822,13 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
            !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) {
                if (dev_priv->display.cdclk.hw.vco != vco)
                        adlp_cdclk_pll_crawl(dev_priv, vco);
-       } else if (DISPLAY_VER(dev_priv) >= 11)
+       } else if (DISPLAY_VER(dev_priv) >= 11) {
+               /* wa_15010685871: dg2, mtl */
+               if (pll_enable_wa_needed(dev_priv))
+                       dg2_cdclk_squash_program(dev_priv, 0);
+
                icl_cdclk_pll_update(dev_priv, vco);
-       else
+       } else
                bxt_cdclk_pll_update(dev_priv, vco);
 
        waveform = cdclk_squash_waveform(dev_priv, cdclk);