KVM: arm64: Enforce absence of FEAT_FGT2 on FGT2 registers

Similarly to the FEAT_FGT registers, add the dependency between
the registers and the controlling feature.

WHile we're at it, add the missing checks for the RES0 vs valid
bit overlap.

Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/kvm/config.c b/arch/arm64/kvm/config.c
index 887e7338fffec9e653247ae3a37bf64780ff5be5..824ad91b4616d50b70e71fead22f11788d138427 100644 (file)
--- a/arch/arm64/kvm/config.c
+++ b/arch/arm64/kvm/config.c
@@ -212,6 +212,7 @@ struct reg_feat_map_desc {
 #define FEAT_SSBS              ID_AA64PFR1_EL1, SSBS, IMP
 #define FEAT_TIDCP1            ID_AA64MMFR1_EL1, TIDCP1, IMP
 #define FEAT_FGT               ID_AA64MMFR0_EL1, FGT, IMP
+#define FEAT_FGT2              ID_AA64MMFR0_EL1, FGT, FGT2
 #define FEAT_MTPMU             ID_AA64DFR0_EL1, MTPMU, IMP
 
 static bool not_feat_aa64el3(struct kvm *kvm)
@@ -788,6 +789,9 @@ static const struct reg_bits_to_feat_map hfgitr2_feat_map[] = {
        NEEDS_FEAT(HFGITR2_EL2_TSBCSYNC, FEAT_TRBEv1p1)
 };
 
+static const DECLARE_FEAT_MAP_FGT(hfgitr2_desc, hfgitr2_masks,
+                                 hfgitr2_feat_map, FEAT_FGT2);
+
 static const struct reg_bits_to_feat_map hfgrtr2_feat_map[] = {
        NEEDS_FEAT(HFGRTR2_EL2_nPFAR_EL1, FEAT_PFAR),
        NEEDS_FEAT(HFGRTR2_EL2_nERXGSR_EL1, FEAT_RASv2),
@@ -807,6 +811,9 @@ static const struct reg_bits_to_feat_map hfgrtr2_feat_map[] = {
        NEEDS_FEAT(HFGRTR2_EL2_nRCWSMASK_EL1, FEAT_THE),
 };
 
+static const DECLARE_FEAT_MAP_FGT(hfgrtr2_desc, hfgrtr2_masks,
+                                 hfgrtr2_feat_map, FEAT_FGT2);
+
 static const struct reg_bits_to_feat_map hfgwtr2_feat_map[] = {
        NEEDS_FEAT(HFGWTR2_EL2_nPFAR_EL1, FEAT_PFAR),
        NEEDS_FEAT(HFGWTR2_EL2_nACTLRALIAS_EL1  |
@@ -825,6 +832,9 @@ static const struct reg_bits_to_feat_map hfgwtr2_feat_map[] = {
        NEEDS_FEAT(HFGWTR2_EL2_nRCWSMASK_EL1, FEAT_THE),
 };
 
+static const DECLARE_FEAT_MAP_FGT(hfgwtr2_desc, hfgwtr2_masks,
+                                 hfgwtr2_feat_map, FEAT_FGT2);
+
 static const struct reg_bits_to_feat_map hdfgrtr2_feat_map[] = {
        NEEDS_FEAT(HDFGRTR2_EL2_nMDSELR_EL1, FEAT_Debugv8p9),
        NEEDS_FEAT(HDFGRTR2_EL2_nPMECR_EL1, feat_ebep_pmuv3_ss),
@@ -855,6 +865,9 @@ static const struct reg_bits_to_feat_map hdfgrtr2_feat_map[] = {
        NEEDS_FEAT(HDFGRTR2_EL2_nTRBMPAM_EL1, feat_trbe_mpam),
 };
 
+static const DECLARE_FEAT_MAP_FGT(hdfgrtr2_desc, hdfgrtr2_masks,
+                                 hdfgrtr2_feat_map, FEAT_FGT2);
+
 static const struct reg_bits_to_feat_map hdfgwtr2_feat_map[] = {
        NEEDS_FEAT(HDFGWTR2_EL2_nMDSELR_EL1, FEAT_Debugv8p9),
        NEEDS_FEAT(HDFGWTR2_EL2_nPMECR_EL1, feat_ebep_pmuv3_ss),
@@ -883,6 +896,10 @@ static const struct reg_bits_to_feat_map hdfgwtr2_feat_map[] = {
        NEEDS_FEAT(HDFGWTR2_EL2_nTRBMPAM_EL1, feat_trbe_mpam),
 };
 
+static const DECLARE_FEAT_MAP_FGT(hdfgwtr2_desc, hdfgwtr2_masks,
+                                 hdfgwtr2_feat_map, FEAT_FGT2);
+
+
 static const struct reg_bits_to_feat_map hcrx_feat_map[] = {
        NEEDS_FEAT(HCRX_EL2_PACMEn, feat_pauth_lr),
        NEEDS_FEAT(HCRX_EL2_EnFPM, FEAT_FPMR),
@@ -1159,6 +1176,11 @@ void __init check_feature_map(void)
        check_reg_desc(&hdfgrtr_desc);
        check_reg_desc(&hdfgwtr_desc);
        check_reg_desc(&hafgrtr_desc);
+       check_reg_desc(&hfgrtr2_desc);
+       check_reg_desc(&hfgwtr2_desc);
+       check_reg_desc(&hfgitr2_desc);
+       check_reg_desc(&hdfgrtr2_desc);
+       check_reg_desc(&hdfgwtr2_desc);
        check_feat_map(hcrx_feat_map, ARRAY_SIZE(hcrx_feat_map),
                       __HCRX_EL2_RES0, "HCRX_EL2");
        check_feat_map(hcr_feat_map, ARRAY_SIZE(hcr_feat_map),
@@ -1289,25 +1311,20 @@ void compute_fgu(struct kvm *kvm, enum fgt_group_id fgt)
                                             0, NEVER_FGU);
                break;
        case HFGRTR2_GROUP:
-               val |= compute_res0_bits(kvm, hfgrtr2_feat_map,
-                                        ARRAY_SIZE(hfgrtr2_feat_map),
-                                        0, NEVER_FGU);
-               val |= compute_res0_bits(kvm, hfgwtr2_feat_map,
-                                        ARRAY_SIZE(hfgwtr2_feat_map),
-                                        0, NEVER_FGU);
+               val |= compute_reg_res0_bits(kvm, &hfgrtr2_desc,
+                                            0, NEVER_FGU);
+               val |= compute_reg_res0_bits(kvm, &hfgwtr2_desc,
+                                            0, NEVER_FGU);
                break;
        case HFGITR2_GROUP:
-               val |= compute_res0_bits(kvm, hfgitr2_feat_map,
-                                        ARRAY_SIZE(hfgitr2_feat_map),
-                                        0, NEVER_FGU);
+               val |= compute_reg_res0_bits(kvm, &hfgitr2_desc,
+                                            0, NEVER_FGU);
                break;
        case HDFGRTR2_GROUP:
-               val |= compute_res0_bits(kvm, hdfgrtr2_feat_map,
-                                        ARRAY_SIZE(hdfgrtr2_feat_map),
-                                        0, NEVER_FGU);
-               val |= compute_res0_bits(kvm, hdfgwtr2_feat_map,
-                                        ARRAY_SIZE(hdfgwtr2_feat_map),
-                                        0, NEVER_FGU);
+               val |= compute_reg_res0_bits(kvm, &hdfgrtr2_desc,
+                                            0, NEVER_FGU);
+               val |= compute_reg_res0_bits(kvm, &hdfgwtr2_desc,
+                                            0, NEVER_FGU);
                break;
        default:
                BUG();
@@ -1346,33 +1363,23 @@ void get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg, u64 *res0, u64 *r
                *res1 = HAFGRTR_EL2_RES1;
                break;
        case HFGRTR2_EL2:
-               *res0 = compute_res0_bits(kvm, hfgrtr2_feat_map,
-                                         ARRAY_SIZE(hfgrtr2_feat_map), 0, 0);
-               *res0 |= hfgrtr2_masks.res0;
+               *res0 = compute_reg_res0_bits(kvm, &hfgrtr2_desc, 0, 0);
                *res1 = HFGRTR2_EL2_RES1;
                break;
        case HFGWTR2_EL2:
-               *res0 = compute_res0_bits(kvm, hfgwtr2_feat_map,
-                                         ARRAY_SIZE(hfgwtr2_feat_map), 0, 0);
-               *res0 |= hfgwtr2_masks.res0;
+               *res0 = compute_reg_res0_bits(kvm, &hfgwtr2_desc, 0, 0);
                *res1 = HFGWTR2_EL2_RES1;
                break;
        case HFGITR2_EL2:
-               *res0 = compute_res0_bits(kvm, hfgitr2_feat_map,
-                                         ARRAY_SIZE(hfgitr2_feat_map), 0, 0);
-               *res0 |= hfgitr2_masks.res0;
+               *res0 = compute_reg_res0_bits(kvm, &hfgitr2_desc, 0, 0);
                *res1 = HFGITR2_EL2_RES1;
                break;
        case HDFGRTR2_EL2:
-               *res0 = compute_res0_bits(kvm, hdfgrtr2_feat_map,
-                                         ARRAY_SIZE(hdfgrtr2_feat_map), 0, 0);
-               *res0 |= hdfgrtr2_masks.res0;
+               *res0 = compute_reg_res0_bits(kvm, &hdfgrtr2_desc, 0, 0);
                *res1 = HDFGRTR2_EL2_RES1;
                break;
        case HDFGWTR2_EL2:
-               *res0 = compute_res0_bits(kvm, hdfgwtr2_feat_map,
-                                         ARRAY_SIZE(hdfgwtr2_feat_map), 0, 0);
-               *res0 |= hdfgwtr2_masks.res0;
+               *res0 = compute_reg_res0_bits(kvm, &hdfgwtr2_desc, 0, 0);
                *res1 = HDFGWTR2_EL2_RES1;
                break;
        case HCRX_EL2: