net: phy: dp83867: fix speed 10 in sgmii mode

For supporting 10Mps speed in SGMII mode DP83867_10M_SGMII_RATE_ADAPT bit
of DP83867_10M_SGMII_CFG register has to be cleared by software.
That does not affect speeds 100 and 1000 so can be done on init.

Signed-off-by: Max Uvarov <muvarov@gmail.com>
Cc: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index fd35131a0c39fd714e401725c8942ba239f21e8a..1091a625bf4ceafe4dc237a24502f0fa1320b71f 100644 (file)
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -30,6 +30,8 @@
 #define DP83867_STRAP_STS1     0x006E
 #define DP83867_RGMIIDCTL      0x0086
 #define DP83867_IO_MUX_CFG     0x0170
+#define DP83867_10M_SGMII_CFG   0x016F
+#define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
 
 #define DP83867_SW_RESET       BIT(15)
 #define DP83867_SW_RESTART     BIT(14)
@@ -277,6 +279,21 @@ static int dp83867_config_init(struct phy_device *phydev)
                                       DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL);
        }
 
+       if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
+               /* For support SPEED_10 in SGMII mode
+                * DP83867_10M_SGMII_RATE_ADAPT bit
+                * has to be cleared by software. That
+                * does not affect SPEED_100 and
+                * SPEED_1000.
+                */
+               ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
+                                    DP83867_10M_SGMII_CFG,
+                                    DP83867_10M_SGMII_RATE_ADAPT_MASK,
+                                    0);
+               if (ret)
+                       return ret;
+       }
+
        /* Enable Interrupt output INT_OE in CFG3 register */
        if (phy_interrupt_is_valid(phydev)) {
                val = phy_read(phydev, DP83867_CFG3);