* "last user address" is set even if bootp is used without parameters
(and it uses default address).
+======================================================================
+Modifications for 0.9.2:
+======================================================================
+
+* Fix confusion of CFG_FLASH_BASE and CFG_MONITOR_BASE in many source
+ files (maybe I've missed a few places, be careful!)
+
+* Fix a few relocation problems
+
+* All major functions working on PCU E
+
======================================================================
Modifications for 0.9.1:
======================================================================
size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
+#endif
flash_info[0].size = size_b0;
ppc/vsprintf.o (.text)
ppc/crc32.o (.text)
ppc/zlib.o (.text)
-
+/* XXX ?
. = env_offset;
+*/
common/environment.o(.text)
*(.text)
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
+#endif
if (size_b1) {
memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[1]);
+#endif
} else {
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[1].sector_count = -1;
/*int flash_write (uchar *, ulong, ulong); */
/*flash_info_t *addr2info (ulong); */
-/* static int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt); */
static void flash_get_offsets (ulong base, flash_info_t *info);
-/*static int flash_protect (int flag, ulong from, ulong to, flash_info_t *info); */
/*-----------------------------------------------------------------------
*/
&flash_info[0]);
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
+#endif
if (size_b1) {
memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[1]);
+#endif
} else {
memctl->memc_br1 = 0; /* invalidate bank */
return (size_b0 + size_b1);
}
-/*-----------------------------------------------------------------------
- * Check or set protection status for monitor sectors
- *
- * The monitor always occupies the _first_ part of the _first_ Flash bank.
- */
-/*static int flash_protect (int flag, ulong from, ulong to, flash_info_t *info)
-{
- ulong b_end = info->start[0] + info->size - 1;
- int rc = 0;
- int first = -1;
- int last = -1;
- int i;
-
- if (to < info->start[0]) {
- return (0);
- }
-
- for (i=0; i<info->sector_count; ++i) {
- ulong end;
- short s_end;
-
- s_end = info->sector_count - 1;
-
- end = (i == s_end) ? b_end : info->start[i + 1] - 1;
-
- if (from > end) {
- continue;
- }
- if (to < info->start[i]) {
- continue;
- }
-
- if (from == info->start[i]) {
- first = i;
- if (last < 0) {
- last = s_end;
- }
- }
- if (to == end) {
- last = i;
- if (first < 0) {
- first = 0;
- }
- }
- }
-
- for (i=first; i<=last; ++i) {
- if (flag & FLAG_PROTECT_CLEAR) {
- info->protect[i] = 0;
- } else if (flag & FLAG_PROTECT_SET) {
- info->protect[i] = 1;
- }
- if (info->protect[i]) {
- rc = 1;
- }
- }
- return (rc);
-}
- */
-
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t *info)
/*-----------------------------------------------------------------------
*/
-/*flash_info_t *addr2info (ulong addr)
-{
- flash_info_t *info;
- int i;
-
- for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) {
- if ((addr >= info->start[0]) &&
- (addr < (info->start[0] + info->size)) ) {
- return (info);
- }
- }
-
- return (NULL);
-}
-*/
-/*-----------------------------------------------------------------------
- * Copy memory to flash.
- * Make sure all target addresses are within Flash bounds,
- * and no protected sectors are hit.
- * Returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - target range includes protected sectors
- * 8 - target address not in Flash memory
- */
-
-/*int flash_write (uchar *src, ulong addr, ulong cnt)
-{
- int i;
- ulong end = addr + cnt - 1;
- flash_info_t *info_first = addr2info (addr);
- flash_info_t *info_last = addr2info (end );
- flash_info_t *info;
-
- if (cnt == 0) {
- return (0);
- }
-
- if (!info_first || !info_last) {
- return (8);
- }
-
- for (info = info_first; info <= info_last; ++info) {
- ulong b_end = info->start[0] + info->size;*/ /* bank end addr */
-/* short s_end = info->sector_count - 1;
- for (i=0; i<info->sector_count; ++i) {
- ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
-
- if ((end >= info->start[i]) && (addr < e_addr) &&
- (info->protect[i] != 0) ) {
- return (4);
- }
- }
- }
-
-*/ /* finally write data to flash */
-/* for (info = info_first; info <= info_last && cnt>0; ++info) {
- ulong len;
-
- len = info->start[0] + info->size - addr;
- if (len > cnt)
- len = cnt;
- if ((i = write_buff(info, src, addr, len)) != 0) {
- return (i);
- }
- cnt -= len;
- addr += len;
- src += len;
- }
- return (0);
-}
-*/
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
+#endif
if (size_b1) {
memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[1]);
+#endif
} else {
memctl->memc_br1 = 0; /* invalidate bank */
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
+#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[1]);
+#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
/* Setup offsets */
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* Monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
+#endif
size_b1 = 0 ;
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE,CFG_FLASH_BASE+CFG_MONITOR_LEN-1, &flash_info[0]);
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+ &flash_info[0]);
+#endif
if (size_b1)
{
//memctl->memc_br1 = CFG_BR1_PRELIM;
/* Re-do sizing to get full correct info */
- size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), &flash_info[1]);
+ size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+ &flash_info[1]);
flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, CFG_FLASH_BASE+CFG_MONITOR_LEN-1, &flash_info[1]);
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+ &flash_info[1]);
+#endif
}
else
{
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
+#endif
flash_info[0].size = size;
flash_info[0].size = size;
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
+#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_info[0].size = size_b0;
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
+#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $^
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Lantec board (based on TQM8xxL config).
+#
+
+TEXT_BASE = 0x40000000
--- /dev/null
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Derived from ../tqm8xx/flash.c
+ * [Torsten Stevens, FHG IMS; Bruno Achauer, Exet AG]
+ */
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef CFG_ENV_ADDR
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef CFG_ENV_SIZE
+# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+# endif
+# ifndef CFG_ENV_SECT_SIZE
+# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
+# endif
+#endif
+
+/*---------------------------------------------------------------------*/
+#undef DEBUG_FLASH
+
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ unsigned long size_b0, size_b1;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0: "
+ "ID 0x%lx, Size = 0x%08lx = %ld MB\n",
+ flash_info[0].flash_id,
+ size_b0, size_b0<<20);
+ }
+
+ DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE5_PRELIM);
+
+ size_b1 = flash_get_size((vu_long *)FLASH_BASE5_PRELIM, &flash_info[1]);
+
+ DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+ if (size_b1 > size_b0) {
+ printf ("## ERROR: "
+ "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+ size_b1, size_b1<<20,
+ size_b0, size_b0<<20
+ );
+ flash_info[0].flash_id = FLASH_UNKNOWN;
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[0].sector_count = -1;
+ flash_info[1].sector_count = -1;
+ flash_info[0].size = 0;
+ flash_info[1].size = 0;
+ return (0);
+ }
+
+ DEBUGF ("## Before remap: "
+ "BR0: 0x%08x OR0: 0x%08x "
+ "BR1: 0x%08x OR1: 0x%08x\n",
+ memctl->memc_br0, memctl->memc_or0,
+ memctl->memc_br1, memctl->memc_or1);
+
+ /* Remap FLASH according to real size */
+ memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+ memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | \
+ BR_MS_GPCM | BR_PS_32 | BR_V;
+
+ DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n",
+ memctl->memc_br0, memctl->memc_or0);
+
+ /* Re-do sizing to get full correct info */
+ size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+ &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+ &flash_info[0]);
+#endif
+
+ if (size_b1) {
+ memctl->memc_or5 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+ memctl->memc_br5 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+ BR_MS_GPCM | BR_PS_32 | BR_V;
+
+ DEBUGF("## BR5: 0x%08x OR5: 0x%08x\n",
+ memctl->memc_br5, memctl->memc_or5);
+
+ /* Re-do sizing to get full correct info */
+ size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+ &flash_info[1]);
+
+ flash_info[1].size = size_b1;
+
+ flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+ &flash_info[1]);
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+ &flash_info[1]);
+#endif
+ } else {
+ memctl->memc_br5 = 0; /* invalidate bank */
+ memctl->memc_or5 = 0; /* invalidate bank */
+
+ DEBUGF("## DISABLE BR5: 0x%08x OR5: 0x%08x\n",
+ memctl->memc_br5, memctl->memc_or5);
+
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[1].sector_count = -1;
+ flash_info[1].size = 0;
+ }
+
+ DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+ return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+
+ /* set up sector start address table */
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00008000;
+ info->start[2] = base + 0x0000C000;
+ info->start[3] = base + 0x00010000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00020000) - 0x00060000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00008000;
+ info->start[i--] = base + info->size - 0x0000C000;
+ info->start[i--] = base + info->size - 0x00010000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00020000;
+ }
+ }
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ short i;
+ ulong value;
+ ulong base = (ulong)addr;
+
+
+ /* Write auto select command: read Manufacturer ID */
+ addr[0x0555] = 0x00AA00AA;
+ addr[0x02AA] = 0x00550055;
+ addr[0x0555] = 0x00900090;
+
+ value = addr[0];
+
+ switch (value) {
+ case AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr[1]; /* device ID */
+
+ switch (value) {
+ case AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+#if 0 /* enable when device IDs are available */
+ case AMD_ID_LV320T:
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 67;
+ info->size = 0x00800000;
+ break; /* => 8 MB */
+
+ case AMD_ID_LV320B:
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 67;
+ info->size = 0x00800000;
+ break; /* => 8 MB */
+#endif
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* set up sector start address table */
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00008000;
+ info->start[2] = base + 0x0000C000;
+ info->start[3] = base + 0x00010000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00020000) - 0x00060000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00008000;
+ info->start[i--] = base + info->size - 0x0000C000;
+ info->start[i--] = base + info->size - 0x00010000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00020000;
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr = (volatile unsigned long *)(info->start[i]);
+ info->protect[i] = addr[2] & 1;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr = (volatile unsigned long *)info->start[0];
+
+ *addr = 0x00F000F0; /* reset bank */
+ }
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ vu_long *addr = (vu_long*)(info->start[0]);
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return;
+ }
+
+ if ((info->flash_id == FLASH_UNKNOWN) ||
+ (info->flash_id > FLASH_AMD_COMP)) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[0x0555] = 0x00AA00AA;
+ addr[0x02AA] = 0x00550055;
+ addr[0x0555] = 0x00800080;
+ addr[0x0555] = 0x00AA00AA;
+ addr[0x02AA] = 0x00550055;
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr = (vu_long*)(info->start[sect]);
+ addr[0] = 0x00300030;
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+
+ start = get_timer (0);
+ last = start;
+ addr = (vu_long*)(info->start[l_sect]);
+ while ((addr[0] & 0x00800080) != 0x00800080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+DONE:
+ /* reset to read mode */
+ addr = (volatile unsigned long *)info->start[0];
+ addr[0] = 0x00F000F0; /* reset bank */
+
+ printf (" done\n");
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ vu_long *addr = (vu_long*)(info->start[0]);
+ ulong start;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[0x0555] = 0x00AA00AA;
+ addr[0x02AA] = 0x00550055;
+ addr[0x0555] = 0x00A000A0;
+
+ *((vu_long *)dest) = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
--- /dev/null
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2001
+ * Torsten Stevens, FHG IMS, stevens@ims.fhg.de
+ * Bruno Achauer, Exet AG, bruno@exet-ag.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Derived from ../tqm8xx/tqm8xx.c
+ */
+
+#include <ppcboot.h>
+#include "mpc8xx.h"
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define _NOT_USED_ 0xFFFFFFFF
+
+const uint sdram_table[] =
+{
+ /*
+ * Single Read. (Offset 0 in UPMA RAM)
+ */
+ 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+ 0x1ff77c47, /* last */
+ /*
+ * SDRAM Initialization (offset 5 in UPMA RAM)
+ *
+ * This is no UPM entry point. The following definition uses
+ * the remaining space to establish an initialization
+ * sequence, which is executed by a RUN command.
+ *
+ */
+ 0x1ff77c35, 0xefeabc34, 0x1fb57c35, /* last */
+ /*
+ * Burst Read. (Offset 8 in UPMA RAM)
+ */
+ 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+ 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Single Write. (Offset 18 in UPMA RAM)
+ */
+ 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Burst Write. (Offset 20 in UPMA RAM)
+ */
+ 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+ 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, /* last */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Refresh (Offset 30 in UPMA RAM)
+ */
+ 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+ 0xfffffc84, 0xfffffc07, 0xfffffc07, /* last */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Exception. (Offset 3c in UPMA RAM)
+ */
+ 0x7ffffc07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Test TQ ID string (TQM8xx...)
+ * If present, check for "L" type (no second DRAM bank),
+ * otherwise "L" type is assumed as default.
+ *
+ * Return 1 for "L" type, 0 else.
+ */
+
+int checkboard (void)
+{
+ puts("Lantec special edition\n");
+ return 1;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ long int size_b0;
+ int i;
+
+ /*
+ * Configure UPMA for SDRAM
+ */
+ upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+ memctl->memc_mptpr = CFG_MPTPR_1BK_8K /* XXX CFG_MPTPR XXX */;
+
+ /* burst length=4, burst type=sequential, CAS latency=2 */
+ memctl->memc_mar = 0x00000088;
+
+ /*
+ * Map controller bank 3 to the SDRAM bank at preliminary address.
+ */
+ memctl->memc_or3 = CFG_OR3_PRELIM;
+ memctl->memc_br3 = CFG_BR3_PRELIM;
+
+ /* initialize memory address register */
+ memctl->memc_mamr = CFG_MAMR_8COL; /* refresh not enabled yet */
+
+ /* mode initialization (offset 5) */
+ udelay(200); /* 0x80006105 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x05);
+
+ /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
+ udelay(1); /* 0x80006130 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x30);
+ udelay(1); /* 0x80006130 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x30);
+
+ udelay(1); /* 0x80006106 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x06);
+
+ memctl->memc_mamr |= MAMR_PTBE; /* refresh enabled */
+
+ udelay(200);
+
+ /* Need at least 10 DRAM accesses to stabilize */
+ for (i=0; i<10; ++i) {
+ volatile unsigned long *addr = \
+ (volatile unsigned long *)SDRAM_BASE3_PRELIM;
+ unsigned long val;
+
+ val = *(addr + i);
+ *(addr + i) = val;
+ }
+
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ */
+ size_b0 = dram_size (CFG_MAMR_8COL,
+ (ulong *)SDRAM_BASE3_PRELIM,
+ SDRAM_MAX_SIZE);
+
+ memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTBE;
+
+ /*
+ * Final mapping:
+ */
+
+ memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+ memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+ udelay(1000);
+
+ return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ volatile long int *addr;
+ long int cnt, val;
+
+ memctl->memc_mamr = mamr_value;
+
+ for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ *addr = ~cnt;
+ }
+
+ /* write 0 to base address */
+ addr = base;
+ *addr = 0;
+
+ /* check at base address */
+ if ((val = *addr) != 0) {
+ return (0);
+ }
+
+ for (cnt = 1; ; cnt <<= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ val = *addr;
+
+ if (val != (~cnt)) {
+ return (cnt * sizeof(long));
+ }
+ }
+ /* NOTREACHED */
+}
--- /dev/null
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ ppc/ppcstring.o (.text)
+ ppc/vsprintf.o (.text)
+ ppc/crc32.o (.text)
+ ppc/zlib.o (.text)
+
+ . = env_offset;
+ common/environment.o(.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ ppc/vsprintf.o (.text)
+ ppc/crc32.o (.text)
+
+ . = env_offset;
+ common/environment.o(.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
flash_info[0].size = size_b0;
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
+#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[1]);
+#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
addr += size;
}
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
+#endif
return (totsize);
}
#endif
/*---------------------------------------------------------------------*/
-#define DEBUG_FLASH
+#undef DEBUG_FLASH
#ifdef DEBUG_FLASH
#define DEBUGF(fmt,args...) printf(fmt ,##args)
static int write_data (flash_info_t *info, ulong dest, ulong data);
static void flash_get_offsets (ulong base, flash_info_t *info);
+/*-----------------------------------------------------------------------
+ *
+ * The PCU E uses an address map where flash banks are aligned top
+ * down, so that the "first" flash bank ends at top of memory, and
+ * the monitor entry point is at address (0xFFF00100). The second
+ * flash bank is mapped immediately below bank 0.
+ *
+ * This is NOT in conformance to the "official" memory map!
+ *
+ */
+
+#define PCU_MONITOR_BASE ( (flash_info[0].start[0] + flash_info[0].size - 1) \
+ - (0xFFFFFFFF - CFG_MONITOR_BASE) )
+
/*-----------------------------------------------------------------------
*/
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0, size_b1;
+ unsigned long base, size_b0, size_b1;
int i;
/* Init: no FLASHes known */
/* Static FLASH Bank configuration here - FIXME XXX */
+ /*
+ * Warning:
+ *
+ * Since the PCU E memory map assigns flash banks top down,
+ * we swap the numbering later if both banks are equipped,
+ * so they look like a contiguous area of memory.
+ */
DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
memctl->memc_br6, memctl->memc_or6);
/* Remap FLASH according to real size */
+ base = 0 - size_b0;
memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
- memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+ memctl->memc_br0 = (base & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n",
memctl->memc_br0, memctl->memc_or0);
/* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+ size_b0 = flash_get_size((vu_long *)base, &flash_info[0]);
+ base = 0 - size_b0;
flash_info[0].size = size_b0;
+ flash_get_offsets (base, &flash_info[0]);
+
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ PCU_MONITOR_BASE,
+ PCU_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
#ifdef CFG_ENV_IS_IN_FLASH
#endif
if (size_b1) {
+ flash_info_t tmp_info;
+
//XXX memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
-//XXX memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+//XXX memctl->memc_br1 = ((base - size_b1) & BR_BA_MSK) |
memctl->memc_or6 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
- memctl->memc_br6 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
- BR_MS_GPCM | BR_V;
+ memctl->memc_br6 = ((base - size_b1) & BR_BA_MSK) |
+ BR_PS_16 | BR_MS_GPCM | BR_V;
-//XXX DEBUGF("## BR1: 0x%08x OR1: 0x%08x\n",
+//XXX DEBUGF("## New BR1: 0x%08x OR1: 0x%08x\n",
//XXX memctl->memc_br1, memctl->memc_or1);
- DEBUGF("## BR6: 0x%08x OR6: 0x%08x\n",
+ DEBUGF("## New BR6: 0x%08x OR6: 0x%08x\n",
memctl->memc_br6, memctl->memc_or6);
/* Re-do sizing to get full correct info */
- size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+ size_b1 = flash_get_size((vu_long *)(base - size_b1),
&flash_info[1]);
+ base -= size_b1;
- flash_info[1].size = size_b1;
-
- flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+ flash_get_offsets (base, &flash_info[1]);
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
- &flash_info[1]);
+ flash_info[1].size = size_b1;
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
&flash_info[1]);
#endif
+ /*
+ * Swap bank numbers so that addresses are in ascending order
+ */
+ tmp_info = flash_info[0];
+ flash_info[0] = flash_info[1];
+ flash_info[1] = tmp_info;
} else {
memctl->memc_br1 = 0; /* invalidate bank */
flash_info[1].sector_count = -1;
}
+
DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
return (size_b0 + size_b1);
/* set up sector start address table */
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
+ for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
+ info->start[i] = base;
+ base += 8 << 10;
+ }
+ while (base < info->size) { /* 64k regular sectors */
+ info->start[i] = base;
+ base += 64 << 10;
+ ++i;
}
} else {
/* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
+ short n;
+
+ base += info->size;
+ i = info->sector_count;
+ for (n=0; n<8; ++n) {
+ base -= 8 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ while (i > 0) {
+ base -= 64 << 10;
+ --i;
+ info->start[i] = base;
}
}
}
switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+ case FLASH_AMDL322B: printf ("AM29DL322B (32 Mbit, bottom boot sect)\n");
break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ case FLASH_AMDL322T: printf ("AM29DL322T (32 Mbit, top boot sector)\n");
break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+ case FLASH_AMDL323B: printf ("AM29DL323B (32 Mbit, bottom boot sect)\n");
break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ case FLASH_AMDL323T: printf ("AM29DL323T (32 Mbit, top boot sector)\n");
break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+ case FLASH_AMDL324B: printf ("AM29DL324B (32 Mbit, bottom boot sect)\n");
break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+ case FLASH_AMDL324T: printf ("AM29DL324T (32 Mbit, top boot sector)\n");
break;
default: printf ("Unknown Chip Type 0x%lX\n",
info->flash_id);
short i;
ushort value;
vu_short *saddr = (vu_short *)addr;
- ulong base = (ulong)addr;
-
/* Write auto select command: read Manufacturer ID */
saddr[0x0555] = 0x00AA;
info->flash_id = FLASH_MAN_FUJ;
break;
default:
+ DEBUGF("Unknown Manufacturer ID\n");
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
DEBUGF("Device ID @ 0x%08lx: 0x%04x\n", (ulong)(&addr[1]), value);
switch (value) {
- case (AMD_ID_LV400T & 0xFFFF):
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV400B & 0xFFFF):
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV800T & 0xFFFF):
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV800B & 0xFFFF):
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV160T & 0xFFFF):
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 4 MB */
-
- case (AMD_ID_LV160B & 0xFFFF):
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 4 MB */
-#if 0 /* enable when device IDs are available */
- case (AMD_ID_LV320T & 0xFFFF):
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
+
+ case (AMD_ID_DL322T & 0xFFFF):
+ info->flash_id += FLASH_AMDL322T;
+ info->sector_count = 71;
info->size = 0x00400000;
break; /* => 8 MB */
- case (AMD_ID_LV320B & 0xFFFF):
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
+ case (AMD_ID_DL322B & 0xFFFF):
+ info->flash_id += FLASH_AMDL322B;
+ info->sector_count = 71;
+ info->size = 0x00400000;
+ break; /* => 8 MB */
+
+ case (AMD_ID_DL323T & 0xFFFF):
+ info->flash_id += FLASH_AMDL323T;
+ info->sector_count = 71;
+ info->size = 0x00400000;
+ break; /* => 8 MB */
+
+ case (AMD_ID_DL323B & 0xFFFF):
+ info->flash_id += FLASH_AMDL323B;
+ info->sector_count = 71;
+ info->size = 0x00400000;
+ break; /* => 8 MB */
+
+ case (AMD_ID_DL324T & 0xFFFF):
+ info->flash_id += FLASH_AMDL324T;
+ info->sector_count = 71;
+ info->size = 0x00400000;
+ break; /* => 8 MB */
+
+ case (AMD_ID_DL324B & 0xFFFF):
+ info->flash_id += FLASH_AMDL324B;
+ info->sector_count = 71;
info->size = 0x00400000;
break; /* => 8 MB */
-#endif
default:
+ DEBUGF("Unknown Device ID\n");
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
+ flash_get_offsets ((ulong)addr, info);
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
+#if 0
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
saddr = (vu_short *)(info->start[i]);
info->protect[i] = saddr[2] & 1;
+#else
+ info->protect[i] =0;
+#endif
}
if (info->sector_count > CFG_MAX_FLASH_SECT) {
0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
/*
* Single Write. (Offset 18 in UPM RAM)
*/
memctl->memc_mamr = CFG_MAMR; /* refresh not enabled yet */
/* mode initialization (offset 5) */
- udelay(200); /* 0x80006105 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x05);
+// udelay(200); /* 0x80004105 */
+// memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x05);
+ udelay(200); /* 0x8000A105 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(1) | MCR_MAD(0x05);
/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
- udelay(1); /* 0x80006130 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x30);
- udelay(1); /* 0x80006130 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x30);
+// udelay(1); /* 0x80004830 */
+// memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(8) | MCR_MAD(0x30);
+ udelay(1); /* 0x8000A830 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(8) | MCR_MAD(0x30);
- udelay(1); /* 0x80006106 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x06);
+// udelay(1); /* 0x80004106 */
+// memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x06);
+ udelay(1); /* 0x8000A106 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(1) | MCR_MAD(0x06);
reg = memctl->memc_mamr;
reg &= ~MAMR_TLFB_MSK; /* switch timer loop ... */
/* Need at least 10 DRAM accesses to stabilize */
for (i=0; i<10; ++i) {
+// volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE2_PRELIM;
volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE5_PRELIM;
unsigned long val;
/*
* Check Bank 0 Memory Size for re-configuration
*/
+// size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
memctl->memc_mamr = CFG_MAMR | MAMR_PTBE;
}
/* ------------------------------------------------------------------------- */
+
+#define ETH_CFG_BITS (CFG_PB_ETH_MDDIS | CFG_PB_ETH_CFG1 | \
+ CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 )
+
+#define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN | CFG_PB_ETH_RESET)
+
+void reset_phy(void)
+{
+ immap_t *immr = (immap_t *)CFG_IMMR;
+ ulong value;
+
+ /* Configure all needed port pins for GPIO */
+ immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */
+ immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */
+
+ value = immr->im_cpm.cp_pbdat;
+
+ /* Assert Powerdown and Reset signals */
+ value |= CFG_PB_ETH_POWERDOWN;
+ value &= ~(CFG_PB_ETH_RESET);
+
+ /* PHY configuration includes MDDIS and CFG1 ... CFG3 */
+#if CFG_PB_ETH_MDDIS_VALUE
+ value |= CFG_PB_ETH_MDDIS;
+#else
+ value &= ~(CFG_PB_ETH_MDDIS);
+#endif
+#if CFG_PB_ETH_CFG1_VALUE
+ value |= CFG_PB_ETH_CFG1;
+#else
+ value &= ~(CFG_PB_ETH_CFG1);
+#endif
+#if CFG_PB_ETH_CFG2_VALUE
+ value |= CFG_PB_ETH_CFG2;
+#else
+ value &= ~(CFG_PB_ETH_CFG2);
+#endif
+#if CFG_PB_ETH_CFG3_VALUE
+ value |= CFG_PB_ETH_CFG3;
+#else
+ value &= ~(CFG_PB_ETH_CFG3);
+#endif
+
+ /* Drive output signals to initial state */
+ immr->im_cpm.cp_pbdat = value;
+ immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
+ udelay (10000);
+
+ /* De-assert Ethernet Powerdown */
+ immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
+ udelay (10000);
+
+ /* de-assert RESET signal of PHY */
+ immr->im_cpm.cp_pbdat |= CFG_PB_ETH_RESET;
+ udelay (1000);
+}
+
+/* ------------------------------------------------------------------------- */
int i;
/* Init: no FLASHes known */
- for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
- {
+ for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
- if (flash_info[0].flash_id == FLASH_UNKNOWN)
- {
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",size_b0, size_b0<<20);
}
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
+#endif
- if (size_b1)
- {
+ if (size_b1) {
memctl->memc_or1 = CFG_OR1_PRELIM;
memctl->memc_br1 = CFG_BR1_PRELIM;
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[1]);
- }
- else
- {
+ } else {
memctl->memc_or1 = CFG_OR1_PRELIM;
memctl->memc_br1 = CFG_BR1_PRELIM;
{
int i;
- if (info->flash_id == FLASH_UNKNOWN)
- {
+ if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
- switch (info->flash_id & FLASH_VENDMASK)
- {
+ switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
default: printf ("Unknown Vendor "); break;
}
- switch (info->flash_id & FLASH_TYPEMASK)
- {
+ switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
break;
default: printf ("Unknown Chip Type\n");
printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i)
- {
- if ((i % 5) == 0)
- {
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0) {
printf ("\n ");
}
value = addr[0];
- switch (value + (value << 16))
- {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
+ switch (value + (value << 16)) {
+ case AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
+ case FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ break;
}
value = addr[1]; /* device ID */
- switch (value)
- {
- case AMD_ID_F040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
+ switch (value) {
+ case AMD_ID_F040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
}
flash_get_offsets ((ulong)addr, &flash_info[0]);
/* check for protected sectors */
- for (i = 0; i < info->sector_count; i++)
- {
+ for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr = (volatile unsigned long *)(info->start[i]);
/*
* Prevent writes to uninitialized FLASH.
*/
- if (info->flash_id != FLASH_UNKNOWN)
- {
+ if (info->flash_id != FLASH_UNKNOWN) {
addr = (volatile unsigned long *)info->start[0];
*addr = 0xF0F0F0F0; /* reset bank */
}
start = get_timer (0);
last = start;
addr = (vu_long*)(info->start[l_sect]);
- while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
- {
+ while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return;
/* data polling for D7 */
start = get_timer (0);
- while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080))
- {
+ while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
+#endif
if (size_b1) {
memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[1]);
+#endif
} else {
memctl->memc_br1 = 0; /* invalidate bank */
static char *failed = "*** failed ***\n";
+#ifdef CONFIG_PCU_E
+extern flash_info_t flash_info[];
+#endif
#if defined(CFG_ENV_IS_IN_FLASH)
# ifndef CFG_ENV_ADDR
# ifndef CFG_ENV_SIZE
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
# endif
-# if (CFG_ENV_ADDR >= CFG_FLASH_BASE) && \
- (CFG_ENV_ADDR+CFG_ENV_SIZE) < (CFG_FLASH_BASE + CFG_MONITOR_LEN)
+# if (CFG_ENV_ADDR >= CFG_MONITOR_BASE) && \
+ (CFG_ENV_ADDR+CFG_ENV_SIZE) < (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
# define ENV_IS_EMBEDDED
# endif
#endif /* CFG_ENV_IS_IN_FLASH */
-#if ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_FLASH_BASE) || \
- (CFG_ENV_ADDR >= (CFG_FLASH_BASE + CFG_MONITOR_LEN)) ) || \
+#if ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \
+ (CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \
defined(CFG_ENV_IS_IN_NVRAM)
#define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE)
#else
bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */
bd->bi_memsize = dram_size; /* size of DRAM memory in bytes */
- bd->bi_flashstart = CFG_FLASH_BASE; /* start of FLASH memory */
- bd->bi_flashsize = 0; /* size of FLASH memory (PRELIM) */
-
-#if CFG_MONITOR_BASE == CFG_FLASH_BASE
- bd->bi_flashoffset = CFG_MONITOR_LEN; /* reserved area for startup monitor */
-#else
- bd->bi_flashoffset = 0;
-#endif
#ifdef CONFIG_IP860
bd->bi_sramstart = SRAM_BASE; /* start of SRAM memory */
printf (" Now running in RAM - dest_addr = 0x%08lx\n", dest_addr);
#endif
- /* Save a global pointer to the board info struct */
+ /*
+ * Save a global pointer to the board info struct
+ */
bd_ptr = bd ;
- /* Set the monitor function pointer to DPAM init data */
+ /*
+ * Set the monitor function pointer to DPRAM init data
+ * and relocate at least the I/O function pointers
+ */
bd->bi_mon_fnc = &idata->bi_mon_fnc;
+ { ulong addr;
+
+ addr = (ulong)(idata->bi_mon_fnc.getc ) + reloc_off;
+ idata->bi_mon_fnc.getc = (int (*)(void))addr;
+
+ addr = (ulong)(idata->bi_mon_fnc.tstc ) + reloc_off;
+ idata->bi_mon_fnc.tstc = (int (*)(void))addr;
+
+ addr = (ulong)(idata->bi_mon_fnc.putc ) + reloc_off;
+ idata->bi_mon_fnc.putc = (void (*)(const char c))addr;
+
+ addr = (ulong)(idata->bi_mon_fnc.puts ) + reloc_off;
+ idata->bi_mon_fnc.puts = (void (*)(const char *s))addr;
+
+ addr = (ulong)(idata->bi_mon_fnc.printf) + reloc_off;
+ idata->bi_mon_fnc.printf = (void (*)(const char *fmt, ...))addr;
+ }
/*
* We have to relocate the command table manually
puts (failed);
hang();
}
- bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */
+ bd->bi_flashstart = CFG_FLASH_BASE; /* update start of FLASH memory */
+ bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */
+#if defined(CONFIG_PCU_E)
+ bd->bi_flashoffset = 0;
+#elif CFG_MONITOR_BASE == CFG_FLASH_BASE
+ bd->bi_flashoffset = CFG_MONITOR_LEN; /* reserved area for startup monitor */
+#else
+ bd->bi_flashoffset = 0;
+#endif
/* initialize higher level parts of CPU like time base and timers */
cpu_init_r (bd);
defined(CONFIG_IVML24) || \
defined(CONFIG_IP860) || \
defined(CONFIG_LWMON) || \
- defined(CONFIG_RPXSUPER) )
+ defined(CONFIG_RPXSUPER) || \
+ defined(CONFIG_PCU_E) )
# ifdef DEBUG
puts (" Reset Ethernet PHY\n");
# endif
/** LEAVE THIS HERE **/
/* Initialize devices */
- devices_init();
+ devices_init (reloc_off);
/* Initialize the console (after the relocation and devices init) */
console_init_r (reloc_off);
# ifndef CFG_ENV_SIZE
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
# endif
-# if (CFG_ENV_ADDR >= CFG_FLASH_BASE) && \
- (CFG_ENV_ADDR+CFG_ENV_SIZE) <= (CFG_FLASH_BASE + CFG_MONITOR_LEN)
+# if (CFG_ENV_ADDR >= CFG_MONITOR_BASE) && \
+ (CFG_ENV_ADDR+CFG_ENV_SIZE) <= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
# define ENV_IS_EMBEDDED
# endif
#endif /* CFG_ENV_IS_IN_FLASH */
return 0 ;
}
-int devices_init (void)
+int devices_init (ulong relocation_offset)
{
- // Initialize the list
+ int i;
+
+ /* relocate device name pointers */
+ for (i=0; i<(sizeof(stdio_names)/sizeof(char *)); ++i) {
+ stdio_names[i] = (char *)(((ulong)stdio_names[i]) + relocation_offset);
+ }
+
+ /* Initialize the list */
devlist = ListCreate(sizeof(device_t)) ;
- if (devlist == NULL)
- {
+ if (devlist == NULL) {
eputs("Cannot initialize the list of devices!\n");
return -1 ;
}
# ifndef CFG_ENV_SIZE
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
# endif
-# if (CFG_ENV_ADDR >= CFG_FLASH_BASE) && \
- (CFG_ENV_ADDR+CFG_ENV_SIZE) <= (CFG_FLASH_BASE + CFG_MONITOR_LEN)
+# if (CFG_ENV_ADDR >= CFG_MONITOR_BASE) && \
+ (CFG_ENV_ADDR+CFG_ENV_SIZE) <= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
# define ENV_IS_EMBEDDED
# endif
#endif /* CFG_ENV_IS_IN_FLASH */
.section ".ppcenv"
#else
.text
-#endif
+#endif /* FADS, HYMOD */
+
.globl environment
environment:
.globl env_crc
.L_end:
#if defined(CONFIG_FADS) || defined(CONFIG_HYMOD)
.text
-#endif
+#endif /* FADS, HYMOD */
+
.globl env_size
env_size:
.long .L_end - environment
.globl env_offset
.set env_offset, CFG_ENV_OFFSET
-#endif /* CFG_FLASH_ENV_ADDR */
+#endif /* ENV_IS_EMBEDDED */
#LDSCRIPT := board/$(BOARD)/ppcboot.lds.debug
LDSCRIPT := board/$(BOARD)/ppcboot.lds
-CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \
- -D__KERNEL__ -D__powerpc__ \
- -I$(TOPDIR)/include \
- -fno-builtin \
+CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \
+ -D__KERNEL__ -D__powerpc__ -DTEXT_BASE=$(TEXT_BASE) \
+ -I$(TOPDIR)/include \
+ -fno-builtin \
-pipe $(PLATFORM_CPPFLAGS)
CFLAGS := $(CPPFLAGS) -Wall -Wno-uninitialized -Wstrict-prototypes
*----------------------------------------------------------------------*/
#ifndef CONFIG_CU824
#ifndef DEBUG
- lis r3, CFG_FLASH_BASE@h
- ori r3, r3, CFG_FLASH_BASE@l
+ lis r3, CFG_MONITOR_BASE@h
+ ori r3, r3, CFG_MONITOR_BASE@l
addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
mtlr r3
blr
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
-#ifdef CONFIG_CU824
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
-#else
#ifdef DEBUG
lis r4, CFG_SDRAM_BASE@h /* Source Address */
ori r4, r4, CFG_SDRAM_BASE@l
#else
- lis r4, CFG_FLASH_BASE@h /* Source Address */
- ori r4, r4, CFG_FLASH_BASE@l
-#endif
+ lis r4, CFG_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CFG_MONITOR_BASE@l
#endif
lis r5, CFG_MONITOR_LEN@h /* Length in Bytes */
ori r5, r5, CFG_MONITOR_LEN@l
/*
* Fix GOT pointer:
*
- * New GOT-PTR = (old GOT-PTR - CFG_FLASH_BASE) + Destination Address
+ * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
*
* Offset:
*/
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
- lis r4, CFG_FLASH_BASE@h /* Source Address */
- ori r4, r4, CFG_FLASH_BASE@l
+ lis r4, CFG_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CFG_MONITOR_BASE@l
lis r5, CFG_MONITOR_LEN@h /* Length in Bytes */
ori r5, r5, CFG_MONITOR_LEN@l
li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
- * New GOT-PTR = (old GOT-PTR - CFG_FLASH_BASE) + Destination Address
+ * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
*
* Offset:
*/
#define SICR_ENET_CLKRT ((uint)0x00003E00)
#endif /* CONFIG_LWMON */
+/*** PCU E ***********************************************************/
+
+/* The PCU E uses the FEC on a MPC860T for Ethernet */
+
+#ifdef CONFIG_PCU_E
+
+#define FEC_ENET /* use FEC for EThernet */
+#undef SCC_ENET
+
+#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
+#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
+#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
+#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
+#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
+#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
+#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
+#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
+#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
+#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
+#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
+#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
+#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
+
+#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
+
+#endif /* CONFIG_PCU_E */
+
/*** SXNI855T ******************************************************/
#if defined(CONFIG_SXNI855T)
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1
- -- XXX: comment doesn't match code */
+/* FLASH timing */
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \
OR_SCY_5_CLK | OR_TRLX)
#undef CONFIG_WATCHDOG /* watchdog disabled */
-#undef CONFIG_STATUS_LED /* Status LED disabled */
+#define CONFIG_STATUS_LED /* Status LED enabled */
-#define CONFIG_SOFT_I2C /* Software I2C support enabled */
-# define CFG_I2C_SPEED 50000
-# define CFG_I2C_SLAVE 0xFE
-# define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Atmel 24C164 has 16 byte */
- /* page write mode using last */
- /* 4 bits of the address */
-
-#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
-
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_EEPROM | \
- CFG_CMD_DATE ) \
- & ~CFG_CMD_NET
+#define CONFIG_COMMANDS CONFIG_CMD_DFL
#define CONFIG_BOOTP_MASK \
((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
+/* Ethernet hardware configuration done using port pins */
+#define CFG_PB_ETH_MDDIS 0x00000010 /* PB 27 */
+#define CFG_PB_ETH_RESET 0x00000020 /* PB 26 */
+//XXX#define CFG_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */
+//XXX#define CFG_PB_ETH_CFG1 0x00000200 /* PB 22 */
+//XXX#define CFG_PB_ETH_CFG2 0x00000400 /* PB 21 */
+//XXX#define CFG_PB_ETH_CFG3 0x00000800 /* PB 20 */
+#define CFG_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */
+#define CFG_PB_ETH_CFG1 0x00000400 /* PB 21 */
+#define CFG_PB_ETH_CFG2 0x00000200 /* PB 22 */
+#define CFG_PB_ETH_CFG3 0x00000100 /* PB 23 */
+
+/* Ethernet settings:
+ * MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex
+ */
+#define CFG_PB_ETH_MDDIS_VALUE 0
+#define CFG_PB_ETH_CFG1_VALUE 1
+#define CFG_PB_ETH_CFG2_VALUE 1
+#define CFG_PB_ETH_CFG3_VALUE 1
+
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_FLASH_BASE 0xFF800000
+/* this is an ugly hack needed because of the silly non-constant address map */
+#define CFG_FLASH_BASE (0-flash_info[0].size-flash_info[1].size)
+//#define CFG_FLASH_BASE 0xFF000000
+
#if defined(DEBUG)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#endif
-#define CFG_MONITOR_BASE 0xFFF00000 // was: CFG_FLASH_BASE
+#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
#if 1
/* Start port with environment in flash; switch to EEPROM later */
#define CFG_ENV_IS_IN_FLASH 1
-//#define CFG_ENV_ADDR 0xFFFE0000 /* Address of Environment Sector */
-#define CFG_ENV_OFFSET 0x8000
-#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment */
-//#define CFG_ENV_SECT_SIZE 0x20000 /* we have BIG sectors only :-( */
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */
+#define CFG_ENV_ADDR 0xFFFFE000 /* Address of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x2000 /* use the top-most 8k boot sector */
#else
/* Final version: environment in EEPROM */
#define CFG_ENV_IS_IN_EEPROM 1
/*
* MAMR settings for SDRAM
- * 0x30104118 = Timer B period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10,
+ * 0x30104118 = Timer A period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10,
* MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X
- * 0x30904114 = - " - | Periodic Timer B Enable, MAMR_TLFB_4X
+ * 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X
*/
/* periodic timer for refresh */
-#define CFG_MAMR_PTB 48
+#define CFG_MAMR_PTA 0x30 /* = 48 */
-#define CFG_MAMR ( (CFG_MAMR_PTB << MAMR_PTB_SHIFT) | \
+#define CFG_MAMR ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \
MAMR_AMB_TYPE_1 | \
MAMR_G0CLB_A10 | \
MAMR_RLFB_1X | \
*/
int device_register (device_t *dev);
-int devices_init(void);
+int devices_init (ulong);
int devices_done(void);
#endif /* _DEVICES_H_ */
#define AMD_ID_LV320T 0xDEADBEEF /* 29LV320T ID (32 M, top boot sector) */
#define AMD_ID_LV320B 0xDEADBEEF /* 29LV320B ID (32 M, bottom boot sect) */
-#define AMD_ID_DL323T 0x22502250 /* 29DL323T ID (32 M, top boot sector) */
-#define AMD_ID_DL323B 0x22532253 /* 29DL323B ID (32 M, bottom boot sector) */
+#define AMD_ID_DL322T 0x22552255 /* 29DL322T ID (32 M, top boot sector) */
+#define AMD_ID_DL322B 0x22562256 /* 29DL322B ID (32 M, bottom boot sect) */
+#define AMD_ID_DL323T 0x22502250 /* 29DL323T ID (32 M, top boot sector) */
+#define AMD_ID_DL323B 0x22532253 /* 29DL323B ID (32 M, bottom boot sect) */
+#define AMD_ID_DL324T 0x225C225C /* 29DL324T ID (32 M, top boot sector) */
+#define AMD_ID_DL324B 0x225F225F /* 29DL324B ID (32 M, bottom boot sect) */
#define SST_ID_xF200A 0x27892789 /* 39xF200A ID ( 2M = 128K x 16 ) */
#define SST_ID_xF400A 0x27802780 /* 39xF400A ID ( 4M = 256K x 16 ) */
#define FLASH_AM320T 0x0008 /* AMD AM29LV320 */
#define FLASH_AM320B 0x0009
-#define FLASH_SST200A 0x000A /* SST 39xF200A ID ( 2M = 128K x 16 ) */
-#define FLASH_SST400A 0x000B /* SST 39xF400A ID ( 4M = 256K x 16 ) */
-#define FLASH_SST800A 0x000C /* SST 39xF800A ID ( 8M = 512K x 16 ) */
-#define FLASH_SST160A 0x000D /* SST 39xF160A ID ( 16M = 1M x 16 ) */
-
-#define FLASH_STM800AB 0x0011 /* STM M29WF800AB ( 8M = 512K x 16 ) */
-
-#define FLASH_28F400_T 0x0022 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
-#define FLASH_28F400_B 0x0023 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
-
-#define FLASH_INTEL800T 0x0034 /* INTEL 28F800B3T ( 8M = 512K x 16 ) */
-#define FLASH_INTEL800B 0x0035 /* INTEL 28F800B3B ( 8M = 512K x 16 ) */
-#define FLASH_INTEL160T 0x0036 /* INTEL 28F160B3T ( 16M = 1 M x 16 ) */
-#define FLASH_INTEL160B 0x0037 /* INTEL 28F160B3B ( 16M = 1 M x 16 ) */
-#define FLASH_INTEL320T 0x0038 /* INTEL 28F320B3T ( 32M = 2 M x 16 ) */
-#define FLASH_INTEL320B 0x0039 /* INTEL 28F320B3B ( 32M = 2 M x 16 ) */
-#define FLASH_INTEL640T 0x003A /* INTEL 28F320B3T ( 64M = 4 M x 16 ) */
-#define FLASH_INTEL640B 0x003B /* INTEL 28F320B3B ( 64M = 4 M x 16 ) */
-
-#define FLASH_28F320JA3 0x003C /* INTEL 28F320JA3 ( 32M = 128K x 32) */
-#define FLASH_28F640JA3 0x003D /* INTEL 28F640JA3 ( 64M = 128K x 64) */
-#define FLASH_28F128JA3 0x003E /* INTEL 28F128JA3 (128M = 128K x 128) */
-
-#define FLASH_28F008S5 0x0050 /* Intel 28F008S5 ( 1M = 64K x 16 ) */
-#define FLASH_28F016SV 0x0051 /* Intel 28F016SV ( 16M = 512k x 32 ) */
-#define FLASH_28F800_B 0x0053 /* Intel E28F800B ( 1M = ? ) */
-#define FLASH_AM29F800B 0x0054 /* AMD Am29F800BB ( 1M = ? ) */
-#define FLASH_28F320J5 0x0055 /* Intel 28F320J5 ( 4M = 128K x 32 ) */
-#define FLASH_28F160S3 0x0056 /* Intel 28F160S3 ( 16M = 512K x 32 ) */
-#define FLASH_28F320S3 0x0058 /* Intel 28F320S3 ( 32M = 512K x 64 ) */
+#define FLASH_AMDL322T 0x0010 /* AMD AM29DL322 */
+#define FLASH_AMDL322B 0x0011
+#define FLASH_AMDL323T 0x0012 /* AMD AM29DL323 */
+#define FLASH_AMDL323B 0x0013
+#define FLASH_AMDL324T 0x0014 /* AMD AM29DL324 */
+#define FLASH_AMDL324B 0x0015
+
+#define FLASH_SST200A 0x0040 /* SST 39xF200A ID ( 2M = 128K x 16 ) */
+#define FLASH_SST400A 0x0042 /* SST 39xF400A ID ( 4M = 256K x 16 ) */
+#define FLASH_SST800A 0x0044 /* SST 39xF800A ID ( 8M = 512K x 16 ) */
+#define FLASH_SST160A 0x0046 /* SST 39xF160A ID ( 16M = 1M x 16 ) */
+
+#define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */
+
+#define FLASH_28F400_T 0x0062 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
+#define FLASH_28F400_B 0x0063 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
+
+#define FLASH_INTEL800T 0x0074 /* INTEL 28F800B3T ( 8M = 512K x 16 ) */
+#define FLASH_INTEL800B 0x0075 /* INTEL 28F800B3B ( 8M = 512K x 16 ) */
+#define FLASH_INTEL160T 0x0076 /* INTEL 28F160B3T ( 16M = 1 M x 16 ) */
+#define FLASH_INTEL160B 0x0077 /* INTEL 28F160B3B ( 16M = 1 M x 16 ) */
+#define FLASH_INTEL320T 0x0078 /* INTEL 28F320B3T ( 32M = 2 M x 16 ) */
+#define FLASH_INTEL320B 0x0079 /* INTEL 28F320B3B ( 32M = 2 M x 16 ) */
+#define FLASH_INTEL640T 0x007A /* INTEL 28F320B3T ( 64M = 4 M x 16 ) */
+#define FLASH_INTEL640B 0x007B /* INTEL 28F320B3B ( 64M = 4 M x 16 ) */
+
+#define FLASH_28F320JA3 0x007C /* INTEL 28F320JA3 ( 32M = 128K x 32) */
+#define FLASH_28F640JA3 0x007D /* INTEL 28F640JA3 ( 64M = 128K x 64) */
+#define FLASH_28F128JA3 0x007E /* INTEL 28F128JA3 (128M = 128K x 128) */
+
+#define FLASH_28F008S5 0x0080 /* Intel 28F008S5 ( 1M = 64K x 16 ) */
+#define FLASH_28F016SV 0x0081 /* Intel 28F016SV ( 16M = 512k x 32 ) */
+#define FLASH_28F800_B 0x0083 /* Intel E28F800B ( 1M = ? ) */
+#define FLASH_AM29F800B 0x0084 /* AMD Am29F800BB ( 1M = ? ) */
+#define FLASH_28F320J5 0x0085 /* Intel 28F320J5 ( 4M = 128K x 32 ) */
+#define FLASH_28F160S3 0x0086 /* Intel 28F160S3 ( 16M = 512K x 32 ) */
+#define FLASH_28F320S3 0x0088 /* Intel 28F320S3 ( 32M = 512K x 64 ) */
#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
defined(CONFIG_IVML24) || \
defined(CONFIG_IP860) || \
defined(CONFIG_LWMON) || \
- defined(CONFIG_RPXSUPER)
+ defined(CONFIG_RPXSUPER) || \
+ defined(CONFIG_PCU_E)
/* $(BOARD)/$(BOARD).c */
void reset_phy (void);
#endif
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+/***** PCU E **********************************************************/
+#elif defined(CONFIG_PCU_E)
+
+# define STATUS_LED_PAR im_cpm.cp_pbpar
+# define STATUS_LED_DIR im_cpm.cp_pbdir
+# define STATUS_LED_ODR im_cpm.cp_pbodr
+# define STATUS_LED_DAT im_cpm.cp_pbdat
+
+# define STATUS_LED_BIT 0x00010000 /* green LED is on PB.15 */
+# define STATUS_LED_PERIOD (CFG_HZ / 2)
+# define STATUS_LED_STATE STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
+
+# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+
/************************************************************************/
#else
# error Status LED configuration missing
#ifndef __VERSION_H__
#define __VERSION_H__
-#define PPCBOOT_VERSION "ppcboot 0.9.1"
+#define PPCBOOT_VERSION "ppcboot 0.9.2"
#endif /* __VERSION_H__ */
# ifndef CFG_ENV_SIZE
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
# endif
-# if (CFG_ENV_ADDR >= CFG_FLASH_BASE) && \
- (CFG_ENV_ADDR+CFG_ENV_SIZE) <= (CFG_FLASH_BASE + CFG_MONITOR_LEN)
+# if (CFG_ENV_ADDR >= CFG_MONITOR_BASE) && \
+ (CFG_ENV_ADDR+CFG_ENV_SIZE) <= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
# define ENV_IS_EMBEDDED
# endif
#endif /* CFG_ENV_IS_IN_FLASH */
projects / users / rw / ppcboot.git / commitdiff