mmc: dw_mmc-exynos: Add tuning for sdr and ddr timing for USH-I mode

Add tuning for sdr and ddr timing for USH-I mode sdr104/sdr50/ddr50
for host controller.

Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index ab47b018716a283bda3e8cc28c65a4eea936c53c..d46c3439b5083320987a93c1d6bafdffa0f11110 100644 (file)
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -253,6 +253,8 @@ static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
        if (timing == MMC_TIMING_MMC_HS400) {
                dqs |= DATA_STROBE_EN;
                strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);
+       } else if (timing == MMC_TIMING_UHS_SDR104) {
+               dqs &= 0xffffff00;
        } else {
                dqs &= ~DATA_STROBE_EN;
        }
@@ -312,6 +314,15 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
                if (ios->bus_width == MMC_BUS_WIDTH_8)
                        wanted <<= 1;
                break;
+       case MMC_TIMING_UHS_SDR104:
+       case MMC_TIMING_UHS_SDR50:
+               clksel = (priv->sdr_timing & 0xfff8ffff) |
+                       (priv->ciu_div << 16);
+               break;
+       case MMC_TIMING_UHS_DDR50:
+               clksel = (priv->ddr_timing & 0xfff8ffff) |
+                       (priv->ciu_div << 16);
+               break;
        default:
                clksel = priv->sdr_timing;
        }