phy: exynos5-usbdrd: fix definition of EXYNOS5_FSEL_26MHZ

Using 0x82 seems odd, where everything else is just a sequence.

On E850, this macro isn't used (as a register value), only to assign
its value to the 'extrefclk' variable, which is otherwise unused on
that platform. Older platforms don't appear to support 26MHz in the
first place (since this macro was added for E850).

Furthermore, the downstream driver uses 0x82 to denote
USBPHY_REFCLK_DIFF_26MHZ (whatever that means exactly), but for all the
other values we match downstream's non-DIFF macros.

Update to avoid confusion. No functional change intended.

Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240507-samsung-usb-phy-fixes-v1-4-4ccba5afa7cc@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
index ed4898741c99afae420be7a7babfaf19011fb687..1da7a4881f7264f204a8ae9b96933b0a6f14cc12 100644 (file)
--- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
+++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
@@ -30,7 +30,7 @@
 #define EXYNOS5_FSEL_19MHZ2            0x3
 #define EXYNOS5_FSEL_20MHZ             0x4
 #define EXYNOS5_FSEL_24MHZ             0x5
-#define EXYNOS5_FSEL_26MHZ             0x82
+#define EXYNOS5_FSEL_26MHZ             0x6
 #define EXYNOS5_FSEL_50MHZ             0x7
 
 /* Exynos5: USB 3.0 DRD PHY registers */