extern void cik_update_cg(struct radeon_device *rdev,
                          u32 block, bool enable);
 
-static const struct kv_pt_config_reg didt_config_kv[] =
-{
+static const struct kv_pt_config_reg didt_config_kv[] = {
        { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
        { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
        { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
                                        pi->graphics_level[i].ClkBypassCntl = 2;
                                else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)
                                        pi->graphics_level[i].ClkBypassCntl = 7;
-                               else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)
+                               else if (kv_get_clock_difference(table->entries[i].clk, 20000) < 200)
                                        pi->graphics_level[i].ClkBypassCntl = 6;
-                               else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)
+                               else if (kv_get_clock_difference(table->entries[i].clk, 10000) < 200)
                                        pi->graphics_level[i].ClkBypassCntl = 8;
                                else
                                        pi->graphics_level[i].ClkBypassCntl = 0;
                        if ((new_ps->levels[0].sclk -
                             table->entries[pi->highest_valid].sclk_frequency) >
                            (table->entries[pi->lowest_valid].sclk_frequency -
-                            new_ps->levels[new_ps->num_levels -1].sclk))
+                            new_ps->levels[new_ps->num_levels - 1].sclk))
                                pi->highest_valid = pi->lowest_valid;
                        else
                                pi->lowest_valid =  pi->highest_valid;