drm/amdkfd: hard-code cacheline size for gfx11

This information is not available in ip discovery table.

Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: David Belanger <david.belanger@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 7b826a136ceb9228aa227cbed8e10772af77eb77..d73510c522868f64b964c6f1f22dc9fcdccc72bf 100644 (file)
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -1423,6 +1423,7 @@ err:
 
 
 static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,
+                                                  bool cache_line_size_missing,
                                                   struct kfd_gpu_cache_info *pcache_info)
 {
        struct amdgpu_device *adev = kdev->adev;
@@ -1437,6 +1438,8 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,
                                        CRAT_CACHE_FLAGS_SIMD_CACHE);
                pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2;
                pcache_info[i].cache_line_size = adev->gfx.config.gc_tcp_cache_line_size;
+               if (cache_line_size_missing && !pcache_info[i].cache_line_size)
+                       pcache_info[i].cache_line_size = 128;
                i++;
        }
        /* Scalar L1 Instruction Cache per SQC */
@@ -1449,6 +1452,8 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,
                                        CRAT_CACHE_FLAGS_SIMD_CACHE);
                pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2;
                pcache_info[i].cache_line_size = adev->gfx.config.gc_instruction_cache_line_size;
+               if (cache_line_size_missing && !pcache_info[i].cache_line_size)
+                       pcache_info[i].cache_line_size = 128;
                i++;
        }
        /* Scalar L1 Data Cache per SQC */
@@ -1460,6 +1465,8 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,
                                        CRAT_CACHE_FLAGS_SIMD_CACHE);
                pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2;
                pcache_info[i].cache_line_size = adev->gfx.config.gc_scalar_data_cache_line_size;
+               if (cache_line_size_missing && !pcache_info[i].cache_line_size)
+                       pcache_info[i].cache_line_size = 64;
                i++;
        }
        /* GL1 Data Cache per SA */
@@ -1472,7 +1479,8 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,
                                        CRAT_CACHE_FLAGS_DATA_CACHE |
                                        CRAT_CACHE_FLAGS_SIMD_CACHE);
                pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
-               pcache_info[i].cache_line_size = 0;
+               if (cache_line_size_missing)
+                       pcache_info[i].cache_line_size = 128;
                i++;
        }
        /* L2 Data Cache per GPU (Total Tex Cache) */
@@ -1484,6 +1492,8 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,
                                        CRAT_CACHE_FLAGS_SIMD_CACHE);
                pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
                pcache_info[i].cache_line_size = adev->gfx.config.gc_tcc_cache_line_size;
+               if (cache_line_size_missing && !pcache_info[i].cache_line_size)
+                       pcache_info[i].cache_line_size = 128;
                i++;
        }
        /* L3 Data Cache per GPU */
@@ -1569,6 +1579,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config_v2(struct kfd_dev *kdev,
 int kfd_get_gpu_cache_info(struct kfd_node *kdev, struct kfd_gpu_cache_info **pcache_info)
 {
        int num_of_cache_types = 0;
+       bool cache_line_size_missing = false;
 
        switch (kdev->adev->asic_type) {
        case CHIP_KAVERI:
@@ -1692,10 +1703,17 @@ int kfd_get_gpu_cache_info(struct kfd_node *kdev, struct kfd_gpu_cache_info **pc
                case IP_VERSION(11, 5, 0):
                case IP_VERSION(11, 5, 1):
                case IP_VERSION(11, 5, 2):
+                       /* Cacheline size not available in IP discovery for gc11.
+                        * kfd_fill_gpu_cache_info_from_gfx_config to hard code it
+                        */
+                       cache_line_size_missing = true;
+                       fallthrough;
                case IP_VERSION(12, 0, 0):
                case IP_VERSION(12, 0, 1):
                        num_of_cache_types =
-                               kfd_fill_gpu_cache_info_from_gfx_config(kdev->kfd, *pcache_info);
+                               kfd_fill_gpu_cache_info_from_gfx_config(kdev->kfd,
+                                                                       cache_line_size_missing,
+                                                                       *pcache_info);
                        break;
                default:
                        *pcache_info = dummy_cache_info;