int n;
        int err;
        struct cpu_hw_events *cpuhw;
+       u64 bhrb_filter;
 
        if (!ppmu)
                return -ENOENT;
        err = power_check_constraints(cpuhw, events, cflags, n + 1);
 
        if (has_branch_stack(event)) {
-               cpuhw->bhrb_filter = ppmu->bhrb_filter_map(
+               bhrb_filter = ppmu->bhrb_filter_map(
                                        event->attr.branch_sample_type);
 
-               if (cpuhw->bhrb_filter == -1) {
+               if (bhrb_filter == -1) {
                        put_cpu_var(cpu_hw_events);
                        return -EOPNOTSUPP;
                }
+               cpuhw->bhrb_filter = bhrb_filter;
        }
 
        put_cpu_var(cpu_hw_events);
 
 #define        POWER8_MMCRA_IFM1               0x0000000040000000UL
 #define        POWER8_MMCRA_IFM2               0x0000000080000000UL
 #define        POWER8_MMCRA_IFM3               0x00000000C0000000UL
+#define        POWER8_MMCRA_BHRB_MASK          0x00000000C0000000UL
 
 /*
  * Raw event encoding for PowerISA v2.07 (Power8):
 
 static void power8_config_bhrb(u64 pmu_bhrb_filter)
 {
+       pmu_bhrb_filter &= POWER8_MMCRA_BHRB_MASK;
+
        /* Enable BHRB filter in PMU */
        mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
 }
 
 #define POWER9_MMCRA_IFM1              0x0000000040000000UL
 #define POWER9_MMCRA_IFM2              0x0000000080000000UL
 #define POWER9_MMCRA_IFM3              0x00000000C0000000UL
+#define POWER9_MMCRA_BHRB_MASK         0x00000000C0000000UL
 
 /* Nasty Power9 specific hack */
 #define PVR_POWER9_CUMULUS             0x00002000
 
 static void power9_config_bhrb(u64 pmu_bhrb_filter)
 {
+       pmu_bhrb_filter &= POWER9_MMCRA_BHRB_MASK;
+
        /* Enable BHRB filter in PMU */
        mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
 }