powerpc/603: Switch r0 and r3 in TLB miss handlers

In preparation of next patch that will perform some additional
calculations to replace comparison, switch the use of r0 and r3
as r0 has some limitations in some instructions like 'addi/subi'.

Also remove outdated comments about the meaning of each register.
The registers are used for many things and it would be difficult
to accurately describe all things done with a given register. The
function is now small enough to get a global view without much
description.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://msgid.link/566af5e87685b1a85d3182549c0d520ce2d8877a.1724173828.git.christophe.leroy@csgroup.eu

diff --git a/arch/powerpc/kernel/head_book3s_32.S b/arch/powerpc/kernel/head_book3s_32.S
index 57196883a00e36e869491aab0b1ea027436d8f8f..7995506e7fbd7b752b6407352d0a212e79187e56 100644 (file)
--- a/arch/powerpc/kernel/head_book3s_32.S
+++ b/arch/powerpc/kernel/head_book3s_32.S
@@ -411,39 +411,33 @@ END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
  */
        . = INTERRUPT_INST_TLB_MISS_603
 InstructionTLBMiss:
-/*
- * r0: userspace flag (later scratch)
- * r1: linux style pte ( later becomes ppc hardware pte )
- * r2: ptr to linux-style pte
- * r3: fault address
- */
        /* Get PTE (linux-style) and check access */
-       mfspr   r3,SPRN_IMISS
+       mfspr   r0,SPRN_IMISS
 #ifdef CONFIG_EXECMEM
        lis     r1, TASK_SIZE@h         /* check if kernel address */
-       cmplw   0,r1,r3
+       cmplw   0,r1,r0
 #endif
        mfspr   r2, SPRN_SDR1
        li      r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
        rlwinm  r2, r2, 28, 0xfffff000
 #ifdef CONFIG_EXECMEM
-       li      r0, 3
+       li      r3, 3
        bgt-    112f
        lis     r2, (swapper_pg_dir - PAGE_OFFSET)@ha   /* if kernel address, use */
-       li      r0, 0
+       li      r3, 0
        addi    r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l        /* kernel page table */
 #endif
-112:   rlwimi  r2,r3,12,20,29          /* insert top 10 bits of address */
+112:   rlwimi  r2,r0,12,20,29          /* insert top 10 bits of address */
        lwz     r2,0(r2)                /* get pmd entry */
        rlwinm. r2,r2,0,0,19            /* extract address of pte page */
        beq-    InstructionAddressInvalid       /* return if no mapping */
-       rlwimi  r2,r3,22,20,29          /* insert next 10 bits of address */
+       rlwimi  r2,r0,22,20,29          /* insert next 10 bits of address */
        lwz     r2,0(r2)                /* get linux-style pte */
        andc.   r1,r1,r2                /* check access & ~permission */
        bne-    InstructionAddressInvalid /* return if access not permitted */
        /* Convert linux-style PTE to low word of PPC-style PTE */
 #ifdef CONFIG_EXECMEM
-       rlwimi  r2, r0, 0, 31, 31       /* userspace ? -> PP lsb */
+       rlwimi  r2, r3, 0, 31, 31       /* userspace ? -> PP lsb */
 #endif
        ori     r1, r1, 0xe06           /* clear out reserved bits */
        andc    r1, r2, r1              /* PP = user? 1 : 0 */
@@ -451,7 +445,7 @@ BEGIN_FTR_SECTION
        rlwinm  r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
        mtspr   SPRN_RPA,r1
-       tlbli   r3
+       tlbli   r0
        mfspr   r3,SPRN_SRR1            /* Need to restore CR0 */
        mtcrf   0x80,r3
        rfi
@@ -480,35 +474,29 @@ InstructionAddressInvalid:
  */
        . = INTERRUPT_DATA_LOAD_TLB_MISS_603
 DataLoadTLBMiss:
-/*
- * r0: userspace flag (later scratch)
- * r1: linux style pte ( later becomes ppc hardware pte )
- * r2: ptr to linux-style pte
- * r3: fault address
- */
        /* Get PTE (linux-style) and check access */
-       mfspr   r3,SPRN_DMISS
+       mfspr   r0,SPRN_DMISS
        lis     r1, TASK_SIZE@h         /* check if kernel address */
-       cmplw   0,r1,r3
+       cmplw   0,r1,r0
        mfspr   r2, SPRN_SDR1
        li      r1, _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_READ
        rlwinm  r2, r2, 28, 0xfffff000
-       li      r0, 3
+       li      r3, 3
        bgt-    112f
        lis     r2, (swapper_pg_dir - PAGE_OFFSET)@ha   /* if kernel address, use */
-       li      r0, 0
+       li      r3, 0
        addi    r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l        /* kernel page table */
-112:   rlwimi  r2,r3,12,20,29          /* insert top 10 bits of address */
+112:   rlwimi  r2,r0,12,20,29          /* insert top 10 bits of address */
        lwz     r2,0(r2)                /* get pmd entry */
        rlwinm. r2,r2,0,0,19            /* extract address of pte page */
        beq-    DataAddressInvalid      /* return if no mapping */
-       rlwimi  r2,r3,22,20,29          /* insert next 10 bits of address */
+       rlwimi  r2,r0,22,20,29          /* insert next 10 bits of address */
        lwz     r2,0(r2)                /* get linux-style pte */
        andc.   r1,r1,r2                /* check access & ~permission */
        bne-    DataAddressInvalid      /* return if access not permitted */
        /* Convert linux-style PTE to low word of PPC-style PTE */
        rlwinm  r1,r2,32-9,30,30        /* _PAGE_WRITE -> PP msb */
-       rlwimi  r2,r0,0,30,31           /* userspace ? -> PP */
+       rlwimi  r2,r3,0,30,31           /* userspace ? -> PP */
        rlwimi  r1,r2,32-3,24,24        /* _PAGE_WRITE -> _PAGE_DIRTY */
        xori    r1,r1,_PAGE_DIRTY       /* clear dirty when not rw */
        ori     r1,r1,0xe04             /* clear out reserved bits */
@@ -518,23 +506,23 @@ BEGIN_FTR_SECTION
 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
        mtspr   SPRN_RPA,r1
 BEGIN_MMU_FTR_SECTION
-       li      r0,1
+       li      r3,1
        mfspr   r1,SPRN_SPRG_603_LRU
-       rlwinm  r2,r3,20,27,31          /* Get Address bits 15:19 */
-       slw     r0,r0,r2
-       xor     r1,r0,r1
-       srw     r0,r1,r2
+       rlwinm  r2,r0,20,27,31          /* Get Address bits 15:19 */
+       slw     r3,r3,r2
+       xor     r1,r3,r1
+       srw     r3,r1,r2
        mtspr   SPRN_SPRG_603_LRU,r1
        mfspr   r2,SPRN_SRR1
-       rlwimi  r2,r0,31-14,14,14
+       rlwimi  r2,r3,31-14,14,14
        mtspr   SPRN_SRR1,r2
        mtcrf   0x80,r2
-       tlbld   r3
+       tlbld   r0
        rfi
 MMU_FTR_SECTION_ELSE
        mfspr   r2,SPRN_SRR1            /* Need to restore CR0 */
        mtcrf   0x80,r2
-       tlbld   r3
+       tlbld   r0
        rfi
 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
 DataAddressInvalid:
@@ -560,34 +548,28 @@ DataAddressInvalid:
  */
        . = INTERRUPT_DATA_STORE_TLB_MISS_603
 DataStoreTLBMiss:
-/*
- * r0: userspace flag (later scratch)
- * r1: linux style pte ( later becomes ppc hardware pte )
- * r2: ptr to linux-style pte
- * r3: fault address
- */
        /* Get PTE (linux-style) and check access */
-       mfspr   r3,SPRN_DMISS
+       mfspr   r0,SPRN_DMISS
        lis     r1, TASK_SIZE@h         /* check if kernel address */
-       cmplw   0,r1,r3
+       cmplw   0,r1,r0
        mfspr   r2, SPRN_SDR1
        li      r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT | _PAGE_ACCESSED
        rlwinm  r2, r2, 28, 0xfffff000
-       li      r0, 3
+       li      r3, 3
        bgt-    112f
        lis     r2, (swapper_pg_dir - PAGE_OFFSET)@ha   /* if kernel address, use */
-       li      r0, 0
+       li      r3, 0
        addi    r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l        /* kernel page table */
-112:   rlwimi  r2,r3,12,20,29          /* insert top 10 bits of address */
+112:   rlwimi  r2,r0,12,20,29          /* insert top 10 bits of address */
        lwz     r2,0(r2)                /* get pmd entry */
        rlwinm. r2,r2,0,0,19            /* extract address of pte page */
        beq-    DataAddressInvalid      /* return if no mapping */
-       rlwimi  r2,r3,22,20,29          /* insert next 10 bits of address */
+       rlwimi  r2,r0,22,20,29          /* insert next 10 bits of address */
        lwz     r2,0(r2)                /* get linux-style pte */
        andc.   r1,r1,r2                /* check access & ~permission */
        bne-    DataAddressInvalid      /* return if access not permitted */
        /* Convert linux-style PTE to low word of PPC-style PTE */
-       rlwimi  r2,r0,0,31,31           /* userspace ? -> PP lsb */
+       rlwimi  r2,r3,0,31,31           /* userspace ? -> PP lsb */
        li      r1,0xe06                /* clear out reserved bits & PP msb */
        andc    r1,r2,r1                /* PP = user? 1: 0 */
 BEGIN_FTR_SECTION
@@ -597,23 +579,23 @@ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
        mfspr   r2,SPRN_SRR1            /* Need to restore CR0 */
        mtcrf   0x80,r2
 BEGIN_MMU_FTR_SECTION
-       li      r0,1
+       li      r3,1
        mfspr   r1,SPRN_SPRG_603_LRU
-       rlwinm  r2,r3,20,27,31          /* Get Address bits 15:19 */
-       slw     r0,r0,r2
-       xor     r1,r0,r1
-       srw     r0,r1,r2
+       rlwinm  r2,r0,20,27,31          /* Get Address bits 15:19 */
+       slw     r3,r3,r2
+       xor     r1,r3,r1
+       srw     r3,r1,r2
        mtspr   SPRN_SPRG_603_LRU,r1
        mfspr   r2,SPRN_SRR1
-       rlwimi  r2,r0,31-14,14,14
+       rlwimi  r2,r3,31-14,14,14
        mtspr   SPRN_SRR1,r2
        mtcrf   0x80,r2
-       tlbld   r3
+       tlbld   r0
        rfi
 MMU_FTR_SECTION_ELSE
        mfspr   r2,SPRN_SRR1            /* Need to restore CR0 */
        mtcrf   0x80,r2
-       tlbld   r3
+       tlbld   r0
        rfi
 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)