* "last user address" is set even if bootp is used without parameters
(and it uses default address).
+======================================================================
+Modifications for 1.0.1:
+======================================================================
+
+* Added "tools/scripts" with misc example scripts
+
+* Added BedBug support for 603e core (MPC8260)
+ Patch by Jerry Van Baren: 15 Jun 2001
+
+* Added SPI driver and support for SPI EEPROM
+
+* Modified PCU E configuration: store environment in SPI EEPROM,
+ new memory controller setup for PUMA
+
+* Modified FPS850L configuration to fit in 128 kB
+
+* Re-enabled old code to initialize PLPRCR in board/mbx8xx/mbx8xx.c;
+ reported as necessary by Stefan Balcerczak, 18 Jun 2001
+
======================================================================
Modifications for 1.0.0:
======================================================================
E: <andre.beaudin@colubris.com>
D: PCMCIA, Ethernet, TFTP
+N: Jerry van Baren
+E: <vanbaren@cideas.com>
+D: BedBug port to 603e core (MPC82xx)
+
N: Raphael Bossek
E: raphael.bossek@solutions4linux.de
D: 8xxrom-0.3.0
kernel). Defining CONFIG_STATUS_LED enables this
feature in PPCBoot.
-- CAN Support: CONFIG_CAN_DRVER
+- CAN Support: CONFIG_CAN_DRIVER
Defining CONFIG_CAN_DRIVER enables CAN driver support
on those systems that support this (optional)
feature, like the TQM8xxL modules.
+- SPI Support: CONFIG_SPI
+
+ Enables SPI driver (so far only tested with
+ SPI EEPROM)
+
+ CONFIG_SPI_X
+
+ Enables extended (16-bit) SPI EEPROM addressing.
+ (symmetrical to CONFIG_I2C_X)
+
+
Configuration Settings:
-----------------------
These two #defines specify the offset and size of the
environment area within the total memory of your EEPROM.
+- CFG_SPI_INIT_OFFSET
+
+ Defines offset to the initial SPI buffer area in DPRAM. The
+ area is used at an early stage (ROM part) if the environment
+ is configured to reside in the SPI EEPROM: We need a 520 byte
+ scratch DPRAM area. It is used between the two initialization
+ calls (spi_init_f() and spi_init_r()). A value of 0xB00 seems
+ to be a good choice since it makes it far enough from the
+ start of the data area as well as from the stack pointer.
Please note that the environment is read-only as long as the monitor
has been relocated to RAM and a RAM copy of the environment has been
plprcr &= PLPRCR_MF_MSK; /* isolate MF field */
plprcr |= CFG_PLPRCR; /* reset control bits */
#endif
-#if 0 /* XXX - Just what was this for??? email etheisen@mindspring.com */
+#if 1 /* XXX - Just what was this for??? email etheisen@mindspring.com */
plprcr |= ((speed + refclock / 2) / refclock - 1) << 20;
#endif
immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
puma_load (addr, len);
}
-/*-----------------------------------------------------------------------
- * Board Special Commands: access functions for SPI EEPROM
- */
-#if (CONFIG_COMMANDS & CFG_CMD_BSP)
-
-
-void do_spi (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
-{
- volatile immap_t *immap;
- volatile cpm8xx_t *cp;
- volatile iop8xx_t *iop;
-
- immap = (immap_t *) CFG_IMMR;
- iop = (iop8xx_t *) &immap->im_ioport;
- cp = (cpm8xx_t *) &immap->im_cpm;
-
- /* deactivate Write Protection Pin EEP_WP on EEPROM */
- iop->iop_pcpar &= ~0x0002; /* EEP_WP-Pin is general purpose IO */
- iop->iop_pcdir |= 0x0002; /* EEP_WP-Pin is output */
- iop->iop_pcdat |= 0x0002; /* EEP_WP-Pin high -> not write-protected */
-
- /* Configure and Clear CS for EEPROM */
- cp->cp_pbpar &= ~0x0001;
- cp->cp_pbodr &= ~0x0001;
- cp->cp_pbdat |= 0x0001;
- cp->cp_pbdir |= 0x0001;
-
-
- printf ("*** SPI Init: PBDAT ADR=0x%08x VAL=0x%08x\n",
- (unsigned int) &cp->cp_pbdat, cp->cp_pbdat);
- switch (argc) {
- case 4:
- /* 4 args */
-
- if (strcmp(argv[1],"read") == 0) {
- ulong addr = simple_strtoul(argv[2], NULL, 16);
- ulong cnt = simple_strtoul(argv[3], NULL, 16);
-
- printf ("\nSPI read: addr %08lx count %ld ... ",
- addr, cnt);
-
- spi_init ();
-
- /* Set CS for device */
- cp->cp_pbdat &= ~0x0001;
- printf ("*** do_spi read: Setting CS for PCUE-EEPROM "
- "-> PBDAT = 0x%08x ***\n",
- cp->cp_pbdat);
-
- spi_read ((uchar *)addr, cnt);
-
- /* Clear CS for device */
- cp->cp_pbdat |= 0x0001;
- printf ("*** spi_read: Cleared CS for PCUE-EEPROM "
- "-> PBDAT = 0x%08x ***\n",
- cp->cp_pbdat);
-
- printf ("done\n");
- return;
-
- } else if (strcmp(argv[1],"write") == 0) {
- ulong addr = simple_strtoul(argv[2], NULL, 16);
- ulong cnt = simple_strtoul(argv[3], NULL, 16);
-
- printf ("\nSPI write: addr %08lx count %ld ... ",
- addr, cnt);
-
- spi_init ();
-
- /* Set CS for device */
- cp->cp_pbdat &= ~0x0001;
- printf ("*** do_spi write: Setting CS for PCUE-EEPROM "
- "-> PBDAT = 0x%08x ***\n",
- cp->cp_pbdat);
-
- spi_write((uchar *)addr, cnt);
-
- /* Clear CS for device */
- cp->cp_pbdat |= 0x0001;
- printf ("*** spi_write: Cleared CS for PCUE-EEPROM "
- "-> PBDAT = 0x%08x ***\n",
- cp->cp_pbdat);
-
- printf ("done\n");
- return;
-
- } else {
- printf ("Usage:\n%s\n", cmdtp->usage);
- }
- default:
- break;
- }
- printf ("Usage:\n%s\n", cmdtp->usage);
-
- return;
-}
-
-#endif /* CFG_CMD_BSP */
-
/* ------------------------------------------------------------------------- */
mem_malloc_init (dest_addr);
malloc_bin_reloc (reloc_off);
+#ifdef CONFIG_SPI
+ spi_init_r();
+#endif
+
/* relocate environment function pointers etc. */
env_relocate (reloc_off);
bedbug860_init();
#endif
+#if defined(CONFIG_MPC8240) || defined(CONFIG_MPC8260)
+ /* Processors that are 603e core based */
+ void bedbug603e_init( void );
+
+ bedbug603e_init();
+#endif
+
return;
} /* bedbug_init */
printf ("\nEEPROM read: addr %08lx off %04lx count %ld ... ",
addr, off, cnt);
+#ifndef CONFIG_SPI
eeprom_init ();
+#endif
eeprom_read (off, (uchar *)addr, cnt);
printf ("done\n");
printf ("\nEEPROM write: addr %08lx off %04lx count %ld ... ",
addr, off, cnt);
+#ifndef CONFIG_SPI
eeprom_init ();
+#endif
eeprom_write(off, (uchar *)addr, cnt);
printf ("done\n");
*/
while (offset < end) {
unsigned alen, len, maxlen;
-#ifndef CONFIG_I2C_X
+#if !defined(CONFIG_I2C_X) && !defined(CONFIG_SPI_X)
uchar addr[2];
blk_off = offset & 0xFF; /* block offset */
addr[1] = offset >> 8; /* upper address octet */
addr[2] = blk_off; /* lower address octet */
alen = 3;
-#endif /* CONFIG_I2C_X */
+#endif /* CONFIG_I2C_X, CONFIG_SPI_X */
+#ifdef CFG_I2C_EEPROM_ADDR
addr[0] |= CFG_I2C_EEPROM_ADDR; /* insert device address */
+#endif
maxlen = 0x100 - blk_off;
len = end - offset;
if (len > maxlen)
len = maxlen;
+#ifdef CONFIG_SPI
+ spi_read (addr, alen, buffer, len);
+#else
i2c_read (addr, alen, buffer, len);
+#endif
buffer += len;
offset += len;
}
while (offset < end) {
unsigned alen, len, maxlen;
-#ifndef CONFIG_I2C_X
+#if !defined(CONFIG_I2C_X) && !defined(CONFIG_SPI_X)
uchar addr[2];
blk_off = offset & 0xFF; /* block offset */
addr[1] = offset >> 8; /* upper address octet */
addr[2] = blk_off; /* lower address octet */
alen = 3;
-#endif /* CONFIG_I2C_X */
+#endif /* CONFIG_I2C_X, CONFIG_SPI_X */
+#ifdef CFG_I2C_EEPROM_ADDR
addr[0] |= CFG_I2C_EEPROM_ADDR; /* insert device address */
+#endif
#if defined(CFG_EEPROM_PAGE_WRITE_BITS)
#define PAGE_OFFSET(x) ((x) & ((1 << CFG_EEPROM_PAGE_WRITE_BITS) - 1))
if (len > maxlen)
len = maxlen;
+#ifdef CONFIG_SPI
+ spi_write (addr, alen, buffer, len);
+#else
i2c_write (addr, alen, buffer, len);
+#endif
buffer += len;
offset += len;
}
void eeprom_init (void)
{
#if defined(CONFIG_8xx)
+# if defined(CONFIG_SPI)
+ spi_init_f ();
+# else
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+# endif
#endif
}
/*-----------------------------------------------------------------------
START = start.o kgdb.o
OBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
- interrupts.o ether_scc.o ether_fcc.o i2c.o commproc.o soft_i2c.o
+ interrupts.o ether_scc.o ether_fcc.o i2c.o commproc.o soft_i2c.o \
+ bedbug_603e.o
all: .depend $(START) $(LIB)
--- /dev/null
+/*
+ * Bedbug Functions specific to the MPC603e core
+ */
+
+#include <ppcboot.h>
+#include <command.h>
+#include <linux/ctype.h>
+
+#include <cmd_bedbug.h>
+#include <bedbug/bedbug.h>
+#include <bedbug/regs.h>
+#include <bedbug/ppc.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) && (defined(CONFIG_MPC8240) || defined(CONFIG_MPC8260))
+
+#define MAX_BREAK_POINTS 1
+
+extern CPU_DEBUG_CTX bug_ctx;
+
+void bedbug603e_init __P((void));
+void bedbug603e_do_break __P((cmd_tbl_t*,bd_t*,int,int,char*[]));
+void bedbug603e_break_isr __P((struct pt_regs*));
+int bedbug603e_find_empty __P((void));
+int bedbug603e_set __P((int,unsigned long));
+int bedbug603e_clear __P((int));
+
+\f
+/* ======================================================================
+ * Initialize the global bug_ctx structure for the processor. Clear all
+ * of the breakpoints.
+ * ====================================================================== */
+
+void bedbug603e_init( void )
+{
+ int i;
+ /* -------------------------------------------------- */
+
+ bug_ctx.hw_debug_enabled = 0;
+ bug_ctx.stopped = 0;
+ bug_ctx.current_bp = 0;
+ bug_ctx.regs = NULL;
+
+ bug_ctx.do_break = bedbug603e_do_break;
+ bug_ctx.break_isr = bedbug603e_break_isr;
+ bug_ctx.find_empty = bedbug603e_find_empty;
+ bug_ctx.set = bedbug603e_set;
+ bug_ctx.clear = bedbug603e_clear;
+
+ for( i = 1; i <= MAX_BREAK_POINTS; ++i )
+ (*bug_ctx.clear)( i );
+
+ printf( " BEDBUG Ready\n" );
+
+} /* bedbug_init_breakpoints */
+
+
+\f
+/* ======================================================================
+ * Set/clear/show the hardware breakpoint for the 603e. The "off"
+ * string will disable a specific breakpoint. The "show" string will
+ * display the current breakpoints. Otherwise an address will set a
+ * breakpoint at that address. Setting a breakpoint uses the CPU-specific
+ * set routine which will assign a breakpoint number.
+ * ====================================================================== */
+
+void bedbug603e_do_break (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc,
+ char *argv[])
+{
+ long addr; /* Address to break at */
+ int which_bp; /* Breakpoint number */
+ /* -------------------------------------------------- */
+
+ if (argc < 2)
+ {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return;
+ }
+
+ /* Turn off a breakpoint */
+
+ if( strcmp( argv[ 1 ], "off" ) == 0 )
+ {
+ if( bug_ctx.hw_debug_enabled == 0 )
+ {
+ printf( "No breakpoints enabled\n" );
+ return;
+ }
+
+ which_bp = simple_strtoul( argv[ 2 ], NULL, 10 );
+
+ if( bug_ctx.clear )
+ (*bug_ctx.clear)( which_bp );
+
+ printf( "Breakpoint %d removed\n", which_bp );
+ return;
+ }
+
+ /* Show a list of breakpoints */
+
+ if( strcmp( argv[ 1 ], "show" ) == 0 )
+ {
+ for( which_bp = 1; which_bp <= MAX_BREAK_POINTS; ++which_bp )
+ {
+
+ addr = GET_IABR();
+
+ printf( "Breakpoint [%d]: ", which_bp );
+ if( (addr & 0x00000002) == 0 )
+ printf( "NOT SET\n" );
+ else
+ disppc( (unsigned char *)(addr & 0xFFFFFFFC), 0, 1, bedbug_puts, F_RADHEX );
+ }
+ return;
+ }
+
+ /* Set a breakpoint at the address */
+
+ if(!(( isdigit( argv[ 1 ][ 0 ] )) ||
+ (( argv[ 1 ][ 0 ] >= 'a' ) && ( argv[ 1 ][ 0 ] <= 'f' )) ||
+ (( argv[ 1 ][ 0 ] >= 'A' ) && ( argv[ 1 ][ 0 ] <= 'F' ))))
+ {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return;
+ }
+
+ addr = simple_strtoul( argv[ 1 ], NULL, 16 );
+
+ if(( bug_ctx.set ) && ( which_bp = (*bug_ctx.set)( 0, addr )) > 0 )
+ {
+ printf( "Breakpoint [%d]: ", which_bp );
+ disppc( (unsigned char *)addr, 0, 1, bedbug_puts, F_RADHEX );
+ }
+
+ bug_ctx.bd = bd;
+ return;
+} /* bedbug603e_do_break */
+
+
+\f
+/* ======================================================================
+ * Handle a breakpoint. Enter a mini main loop. Stay in the loop until
+ * the stopped flag in the debug context is cleared.
+ * ====================================================================== */
+
+void bedbug603e_break_isr( struct pt_regs *regs )
+{
+ unsigned long addr; /* Address stopped at */
+ /* -------------------------------------------------- */
+
+ bug_ctx.current_bp = 1;
+ addr = GET_IABR() & 0xFFFFFFFC;
+
+ bedbug_main_loop( addr, regs );
+ return;
+} /* bedbug603e_break_isr */
+
+
+\f
+/* ======================================================================
+ * See if the hardware breakpoint is available.
+ * ====================================================================== */
+
+int bedbug603e_find_empty( void )
+{
+ /* -------------------------------------------------- */
+
+ if( (GET_IABR() && 0x00000002) == 0 )
+ return 1;
+
+ return 0;
+} /* bedbug603e_find_empty */
+
+
+\f
+/* ======================================================================
+ * Set a breakpoint. If 'which_bp' is zero then find an unused breakpoint
+ * number, otherwise reassign the given breakpoint. If hardware debugging
+ * is not enabled, then turn it on via the MSR and DBCR0. Set the break
+ * address in the IABR register.
+ * ====================================================================== */
+
+int bedbug603e_set( int which_bp, unsigned long addr )
+{
+ /* -------------------------------------------------- */
+
+ if(( addr & 0x00000003 ) != 0 )
+ {
+ printf( "Breakpoints must be on a 32 bit boundary\n" );
+ return 0;
+ }
+
+ /* Only look if which_bp == 0, else use which_bp */
+ if(( bug_ctx.find_empty ) && ( !which_bp ) &&
+ ( which_bp = (*bug_ctx.find_empty)()) == 0 )
+ {
+ printf( "All breakpoints in use\n" );
+ return 0;
+ }
+
+ if( which_bp < 1 || which_bp > MAX_BREAK_POINTS )
+ {
+ printf( "Invalid break point # %d\n", which_bp );
+ return 0;
+ }
+
+ if( ! bug_ctx.hw_debug_enabled )
+ {
+ bug_ctx.hw_debug_enabled = 1;
+ }
+
+ SET_IABR( addr | 0x00000002 );
+
+ return which_bp;
+} /* bedbug603e_set */
+
+
+\f
+/* ======================================================================
+ * Disable a specific breakoint by setting the IABR register to zero.
+ * ====================================================================== */
+
+int bedbug603e_clear( int which_bp )
+{
+ /* -------------------------------------------------- */
+
+ if( which_bp < 1 || which_bp > MAX_BREAK_POINTS )
+ {
+ printf( "Invalid break point # (%d)\n", which_bp );
+ return -1;
+ }
+
+ SET_IABR( 0 );
+
+ return 0;
+} /* bedbug603e_clear */
+
+
+/* ====================================================================== */
+#endif
+
*/
1: b 1b
#else
- STD_EXCEPTION(0x1300, InstructionBreakpoint, UnknownException)
+ STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
#endif
STD_EXCEPTION(0x1400, SMI, UnknownException)
_exception(0, regs);
}
+#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
+extern void do_bedbug_breakpoint(struct pt_regs *);
+#endif
+
+void
+DebugException(struct pt_regs *regs)
+{
+
+ printf("Debugger trap at @ %lx\n", regs->nip );
+ show_regs(regs);
+#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
+ do_bedbug_breakpoint( regs );
+#endif
+}
+
/* Probe an address by reading. If not present, return -1, otherwise
* return 0.
*/
#ifdef CONFIG_SPI
+#undef DEBUG
+
+#define SPI_EEPROM_WREN 0x06
+#define SPI_EEPROM_RDSR 0x05
+#define SPI_EEPROM_READ 0x03
+#define SPI_EEPROM_WRITE 0x02
+
+/* ---------------------------------------------------------------
+ * Offset for initial SPI buffers in DPRAM:
+ * We need a 520 byte scratch DPRAM area to use at an early stage.
+ * It is used between the two initialization calls (spi_init_f()
+ * and spi_init_r()).
+ * The value 0xb00 makes it far enough from the start of the data
+ * area (as well as from the stack pointer).
+ * --------------------------------------------------------------- */
+#ifndef CFG_SPI_INIT_OFFSET
+#define CFG_SPI_INIT_OFFSET 0xB00
+#endif
+
+#ifdef DEBUG
+#define DPRINT(a) printf a;
/* -----------------------------------------------
* Helper functions to peek into tx and rx buffers
* ----------------------------------------------- */
printf ("%c", isprint (pc[i]) ? pc[i] : '.');
printf ("\n");
}
+#else /* !DEBUG */
+
+#define DPRINT(a)
+
+#endif /* DEBUG */
/* -------------------
* Function prototypes
* ------------------- */
void spi_init (void);
-ssize_t spi_read (char *, size_t);
-ssize_t spi_write (const char *, size_t);
+ssize_t spi_read (uchar *, int, uchar *, int);
+ssize_t spi_write (uchar *, int, uchar *, int);
+ssize_t spi_xfer (size_t);
/* -------------------
* Variables
* ------------------- */
-static ushort r_tbase, r_rbase;
-static cbd_t *tbdf, *rbdf;
+#define MAX_BUFFER 0x104
-#define MAX_BUFFER 16
-
-/* RX and TX buffer adresses */
-static ulong txbuf;
-static ulong rxbuf;
+/* ----------------------------------------------------------------------
+ * Initially we place the RX and TX buffers at a fixed location in DPRAM!
+ * ---------------------------------------------------------------------- */
+static uchar *rxbuf =
+ (uchar *)&((cpm8xx_t *)&((immap_t *)CFG_IMMR)->im_cpm)->cp_dpmem
+ [CFG_SPI_INIT_OFFSET];
+static uchar *txbuf =
+ (uchar *)&((cpm8xx_t *)&((immap_t *)CFG_IMMR)->im_cpm)->cp_dpmem
+ [CFG_SPI_INIT_OFFSET+MAX_BUFFER];
/* **************************************************************************
*
- * Function: spi_init
+ * Function: spi_init_f
*
- * Description: Init SPI-Controller,
- * allocate and init buffers and buffer descriptors
+ * Description: Init SPI-Controller (ROM part)
*
* return: ---
*
* *********************************************************************** */
-void spi_init ()
+void spi_init_f ()
{
unsigned int dpaddr;
volatile cpic8xx_t *cpi;
volatile cpm8xx_t *cp;
volatile iop8xx_t *iop;
+ volatile cbd_t *tbdf, *rbdf;
immap = (immap_t *) CFG_IMMR;
cpi = (cpic8xx_t *)&immap->im_cpic;
cp->cp_pbpar |= 0x0000000E; /* set bits */
cp->cp_pbpar &= ~0x00000001; /* reset bit */
- printf("*** SPI Init: PBPAR ADR=0x%08x VAL=0x%08x\n",
- (unsigned int)&cp->cp_pbpar, cp->cp_pbpar);
-
/* ----------------------------------------------
* In/Out or per. Function 0/1
* PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO
* ---------------------------------------------- */
cp->cp_pbdir |= 0x0000000F;
- printf("*** SPI Init: PBDIR ADR=0x%08x VAL=0x%08x\n",
- (unsigned int)&cp->cp_pbdir, cp->cp_pbdir);
-
/* ----------------------------------------------
* open drain or active output
* PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO
cp->cp_pbodr |= 0x00000008;
cp->cp_pbodr &= ~0x00000007;
- printf("*** SPI Init: PBODR ADR=0x%08x VAL=0x%04x\n",
- (unsigned int)&cp->cp_pbodr, cp->cp_pbodr);
-
- printf ("*** SPI Init: spi = 0x%08x ***\n", (unsigned int) spi);
-
/* Initialize the parameter ram.
* We need to make sure many things are initialized to zero
*/
dpaddr = CPM_SPI_BASE;
#endif
- printf ("*** SPI Init: dpaddr = 0x%08x ***\n",
- (unsigned int) dpaddr);
-
/* 3 */
/* Set up the SPI parameters in the parameter ram */
- spi->spi_rbase = r_rbase = dpaddr;
- spi->spi_tbase = r_tbase = dpaddr + sizeof (cbd_t);
+ spi->spi_rbase = dpaddr;
+ spi->spi_tbase = dpaddr + sizeof (cbd_t);
/***********IMPORTANT******************/
/* 7 */
/* Set maximum receive size. */
- spi->spi_mrblr = 64;
+ spi->spi_mrblr = MAX_BUFFER;
/* 8 + 9 */
/* tx and rx buffer descriptors */
- tbdf = (cbd_t *) & cp->cp_dpmem[r_tbase];
- rbdf = (cbd_t *) & cp->cp_dpmem[r_rbase];
+ tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
+ rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];
- /* initialize tx and tx bd's */
tbdf->cbd_sc &= ~BD_SC_READY;
rbdf->cbd_sc &= ~BD_SC_EMPTY;
- /* Allocate memory for RX and TX buffers */
- rxbuf = (ulong) malloc (MAX_BUFFER);
- txbuf = (ulong) malloc (MAX_BUFFER);
- printf ("*** SPI Init: rxbuf = 0x%08lx ***\n", rxbuf);
- printf ("*** SPI Init: txbuf = 0x%08lx ***\n", txbuf);
-
/* Set the bd's rx and tx buffer address pointers */
- rbdf->cbd_bufaddr = rxbuf;
- tbdf->cbd_bufaddr = txbuf;
- printf ("*** SPI Init: rbdf->cbd_bufaddr = 0x%08x ***\n",
- rbdf->cbd_bufaddr);
- printf ("*** SPI Init: tbdf->cbd_bufaddr = 0x%08x ***\n",
- tbdf->cbd_bufaddr);
+ rbdf->cbd_bufaddr = (ulong) rxbuf;
+ tbdf->cbd_bufaddr = (ulong) txbuf;
/* 10 + 11 */
cp->cp_spim = 0; /* Mask all SPI events */
return;
}
-#if 0
- /* Shut down SPI */
- cp->cp_spmode = 0;
- cp->cp_spie = 0xff;
- cp->cp_spim = 0;
-#endif
-
-/****************************************************************************
- * spi_write
- **************************************************************************** */
-ssize_t spi_write (const char *buf, size_t count)
+/* **************************************************************************
+ *
+ * Function: spi_init_r
+ *
+ * Description: Init SPI-Controller (RAM part) -
+ * The malloc engine is ready and we can move our buffers to
+ * normal RAM
+ *
+ * return: ---
+ *
+ * *********************************************************************** */
+void spi_init_r ()
{
- volatile immap_t *immap;
volatile cpm8xx_t *cp;
- int tm;
-
- printf("*** spi_write entered ***\n");
-
- if (count > MAX_BUFFER) {
-printf ("Count %d > MAX_BUFFER %d --> truncating\n", count, MAX_BUFFER);
- count = MAX_BUFFER;
- }
+ volatile spi_t *spi;
+ volatile immap_t *immap;
+ volatile cbd_t *tbdf, *rbdf;
- immap = (immap_t *) CFG_IMMR; /* and to internal registers */
+ immap = (immap_t *) CFG_IMMR;
cp = (cpm8xx_t *) &immap->im_cpm;
+ spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
- /* Initialize buffer memory to empty */
- memset ((void *) txbuf, 0, MAX_BUFFER);
- memset ((void *) rxbuf, 0, MAX_BUFFER);
-
- /* copy transmit data from user space to tx buffer */
- memcpy ((void *) txbuf, (void *) buf, count);
-printf ("\nspi_write: txbuf initialized with user space buffer\n");
-memdump ((void *) txbuf, MAX_BUFFER); /* dump of txbuf before tx */
-printf ("spi_write: rxbuf zeroed\n");
-memdump ((void *) rxbuf, MAX_BUFFER); /* dump of rxbuf before tx */
-printf("\n");
+ /* tx and rx buffer descriptors */
+ tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
+ rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];
- /* Setting tx bd status and data length */
- tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP;
- /* tbdf->cbd_sc |= BD_SC_INTRPT; */
- tbdf->cbd_datlen = count;
+ /* Allocate memory for RX and TX buffers */
+ rxbuf = (uchar *) malloc (MAX_BUFFER);
+ txbuf = (uchar *) malloc (MAX_BUFFER);
- printf("*** spi_write: Bytes to be written: %d ***\n", tbdf->cbd_datlen);
+ rbdf->cbd_bufaddr = (ulong) rxbuf;
+ tbdf->cbd_bufaddr = (ulong) txbuf;
- /* Setting rx bd status and data length */
- rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
- rbdf->cbd_datlen = 0; /* rx length = 0 since we are not reading here */
-
- cp->cp_spmode = SPMODE_DIV16 |
- SPMODE_REV |
- SPMODE_MSTR |
- SPMODE_EN |
- SPMODE_LEN(8) | /* 8 Bits per char */
- SPMODE_PM(0x0F) ;
- cp->cp_spim = 0; /* Mask all SPI events */
- cp->cp_spie = SPI_EMASK; /* Clear all SPI events */
+ return;
+}
- /* start spi transfer */
- printf ("*** spi_write: Performing transfer ...\n");
- cp->cp_spcom |= SPI_STR; /* Start transmit */
+/****************************************************************************
+ * Function: spi_write
+ **************************************************************************** */
+ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
+{
+ int i;
- /* --------------------------------
- * Wait for SPI transmit to get out
- * or time out (1 second = 1000 ms)
- * -------------------------------- */
- for (tm=0; tm<1000; ++tm) {
- if (cp->cp_spie & SPI_TXB) { /* Tx Buffer Empty */
-printf("*** spi_write: Tx buffer empty\n");
+ memset(rxbuf, 0, MAX_BUFFER);
+ memset(txbuf, 0, MAX_BUFFER);
+ *txbuf = SPI_EEPROM_WREN; /* write enable */
+ spi_xfer(1);
+ memcpy(txbuf, addr, alen);
+ *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */
+ memcpy(alen + txbuf, buffer, len);
+ spi_xfer(alen + len);
+ /* ignore received data */
+ for (i = 0; i < 1000; i++) {
+ *txbuf = SPI_EEPROM_RDSR; /* read status */
+ txbuf[1] = 0;
+ spi_xfer(2);
+ if (!(rxbuf[1] & 1)) {
break;
}
- if ((tbdf->cbd_sc & BD_SC_READY) == 0) {
-printf("*** spi_write: Tx BD done\n");
- break;
- }
- udelay (1000);
+ udelay(1000);
}
- if (tm >= 1000) {
- printf ("*** spi_write: Time out while writing to SPI!\n");
+ if (i >= 1000) {
+ printf ("*** spi_write: Time out while writing!\n");
}
- printf ("*** spi_write: ... transfer ended\n");
-
- /* Ignore received data */
- printf ("\nspi_write: txbuf after sending\n");
- memdump ((void *) txbuf, MAX_BUFFER);
- printf ("spi_write: received rxbuf in spi_write -> ignore\n");
- memdump ((void *) rxbuf, MAX_BUFFER);
- printf ("\n");
- return count;
+ return len;
}
-
/****************************************************************************
* Function: spi_read
**************************************************************************** */
-ssize_t spi_read (char *buf, size_t count)
+ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
+{
+ memset(rxbuf, 0, MAX_BUFFER);
+ memset(txbuf, 0, MAX_BUFFER);
+ memcpy(txbuf, addr, alen);
+ *txbuf = SPI_EEPROM_READ; /* READ memory array */
+
+ /*
+ * There is a bug in 860T (?) that cuts the last byte of input
+ * if we're reading into DPRAM. The solution we choose here is
+ * to always read len+1 bytes (we have one extra byte at the
+ * end of the buffer).
+ */
+ spi_xfer(alen + len + 1);
+ memcpy(buffer, alen + rxbuf, len);
+
+ return len;
+}
+
+/****************************************************************************
+ * Function: spi_xfer
+ **************************************************************************** */
+ssize_t spi_xfer (size_t count)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
+ volatile spi_t *spi;
+ cbd_t *tbdf, *rbdf;
int tm;
- printf("*** spi_read entered ***\n");
+ DPRINT (("*** spi_xfer entered ***\n"));
- if (count > MAX_BUFFER) {
-printf ("Count %d > MAX_BUFFER %d --> truncating\n", count, MAX_BUFFER);
- count = MAX_BUFFER;
- }
-
- immap = (immap_t *) CFG_IMMR; /* and to internal registers */
+ immap = (immap_t *) CFG_IMMR;
cp = (cpm8xx_t *) &immap->im_cpm;
- /* Initialize buffer memory to empty */
- memset ((void *) txbuf, 0, MAX_BUFFER);
- memset ((void *) rxbuf, 0, MAX_BUFFER);
+ spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
- /* copy transmit data from user space to tx buffer */
- memcpy ((void *) txbuf, (void *) buf, count);
-printf ("\nspi_read: txbuf zeroed\n");
- memdump ((void *) txbuf, MAX_BUFFER); /* dump of txbuf before transmit */
-printf ("spi_read: rxbuf undef (zeroed)\n");
- memdump ((void *) rxbuf, MAX_BUFFER); /* dump of rxbuf before transmit */
- printf ("\n");
+ tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
+ rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];
+
+ /* Set CS for device */
+ cp->cp_pbdat &= ~0x0001;
/* Setting tx bd status and data length */
+ tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP;
tbdf->cbd_datlen = count;
- tbdf->cbd_sc = BD_SC_LAST | BD_SC_WRAP;
- tbdf->cbd_sc |= BD_SC_READY;
- /* Setting rx bd status and data length */
- rbdf->cbd_datlen = count;
- rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
+ DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n",
+ tbdf->cbd_datlen));
- printf ("*** TX BD: "); memdump ((void *) tbdf, sizeof(cbd_t));
- printf ("*** RX BD: "); memdump ((void *) rbdf, sizeof(cbd_t));
- printf ("\n");
+ /* Setting rx bd status and data length */
+ rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
+ rbdf->cbd_datlen = 0; /* rx length has no significance */
cp->cp_spmode = SPMODE_DIV16 |
SPMODE_REV |
cp->cp_spie = SPI_EMASK; /* Clear all SPI events */
/* start spi transfer */
- printf ("*** spi_read: Performing transfer ...\n");
-
- cp->cp_spcom |= SPI_STR;
+ DPRINT (("*** spi_xfer: Performing transfer ...\n"));
+ cp->cp_spcom |= SPI_STR; /* Start transmit */
/* --------------------------------
- * Wait for SPI receive to complete
+ * Wait for SPI transmit to get out
* or time out (1 second = 1000 ms)
* -------------------------------- */
for (tm=0; tm<1000; ++tm) {
- if (cp->cp_spie & SPI_RXB) { /* Rx Buffer closed */
-printf("*** spi_read: Rx buffer closed\n");
+ if (cp->cp_spie & SPI_TXB) { /* Tx Buffer Empty */
+ DPRINT (("*** spi_xfer: Tx buffer empty\n"));
break;
}
- if ((rbdf->cbd_sc & BD_SC_EMPTY) == 0) {
-printf("*** spi_read: Rx BD done\n");
+ if ((tbdf->cbd_sc & BD_SC_READY) == 0) {
+ DPRINT (("*** spi_xfer: Tx BD done\n"));
break;
}
udelay (1000);
}
if (tm >= 1000) {
- printf ("*** spi_read: Time out while reading from SPI!\n");
+ printf ("*** spi_xfer: Time out while xferring to/from SPI!\n");
}
- printf ("*** spi_read: ... transfer ended\n");
+ DPRINT (("*** spi_xfer: ... transfer ended\n"));
- printf ("*** SPI EVENTS: %04X\n", cp->cp_spie);
-
- printf ("*** TX BD: "); memdump ((void *) tbdf, sizeof(cbd_t));
- printf ("*** RX BD: "); memdump ((void *) rbdf, sizeof(cbd_t));
- printf ("\n");
-
-if ((rbdf->cbd_sc & BD_SC_EMPTY) == 0 && (rbdf->cbd_sc & BD_SC_LAST)) {
- printf ("*** Buffer is closed\n");
-}
- printf ("\nspi_read: txbuf after read\n");
- memdump ((void *) txbuf, MAX_BUFFER); /* dump of txbuf before transmit */
- printf ("spi_read: rxbuf after read\n");
- memdump ((void *) rxbuf, MAX_BUFFER); /* dump of rxbuf after transmit */
+#ifdef DEBUG
+ printf ("\nspi_xfer: txbuf after xfer\n");
+ memdump ((void *) txbuf, 16); /* dump of txbuf before transmit */
+ printf ("spi_xfer: rxbuf after xfer\n");
+ memdump ((void *) rxbuf, 16); /* dump of rxbuf after transmit */
printf ("\n");
+#endif
- memcpy ((void *) buf, (void *) rxbuf, count);
+ /* Clear CS for device */
+ cp->cp_pbdat |= 0x0001;
return count;
}
#endif /* CONFIG_SPI */
+
--- /dev/null
+This file contains status information for the port of ppcboot to the
+Galileo Evaluation Board.
+
+Author: Josh Huber <huber@mclx.com>
+ Mission Critical Linux, Inc.
+
+The support for the Galileo Evaluation board is fairly minimal now.
+It's sufficient to boot Linux, but doesn't provide too much more than
+what's required to do this.
+
+Both DUART channels are supported (to use the second one, you have to
+modify the board -- see the schematics for where to solder on the
+devices module). The ethernet ports are supported, and the MPSC is
+supported as a console driver. (keep in mind that the kernel has no
+support for this yet)
+
+There are still occaisonal lockups with the MPSC console driver due to
+(we think!) overrun problems. If you're looking for something stable
+to use for Linux development, consider sticking with the DUART console
+for now.
+
+Automatic memory sizing mostly works. We've had problems with some
+combinations of memory. Please send us email if you're having trouble
+with respect to the memory detection.
+
+Right now, only the 512k boot flash is supported. Support for the
+16MB flash on the devices module is forthcoming. Right now the flash
+is stored at the 256k boundry in flash, wasting a whole sector (64k!)
+for environment data. This isn't really a big deal since we're not
+using the 512k for anything else. (Just ppcboot and the environment)
+
+Finally, here is a sample output session:
+
+PPCBoot 1.0.0-pre1 (Jun 6 2001 - 12:45:11)
+
+Initializing...
+ CPU: MPC7400 (altivec enabled) v2.9
+ Board: EVB64260
+ DRAM: 256 MB
+ FLASH: 512 kB
+ In: serial
+ Out: serial
+ Err: serial
+
+=>
+
+The default configuration should be correct for the evaluation board,
+as it's shipped from Galileo. Keep in mind that the default baudrate
+is set to 38400, 8N1.
+
+Good luck, and make sure to send any bugreports to us (or the
+ppcboot-users list).
+
+Josh
--- /dev/null
+This file contains status information for the port of ppcboot to the
+Motorola mpc74xx series of CPUs.
+
+Author: Josh Huber <huber@mclx.com>
+ Mission Critical Linux, Inc.
+
+Currently the support for these CPUs is pretty minimal, but enough to
+get things going. (much like the support for the Galileo Eval Board)
+
+There is a framework in place to enable the L2 cache, and to program
+the BATs. Currently, there are still problems with the code which
+sets up the L2 cache, so it's not enabled. (IMHO, it shouldn't be
+anyway). Additionally, there is support for enabling the MMU, which
+we also don't do. The BATs are programmed just for the benefit of
+jumping into Linux in a sane configuration.
+
+Most of the code was based on other cpus supported by ppcboot.
+
+If you find any errors in the CPU setup code, please send us a note.
+
+Thanks,
+Josh
#define SPR_SPRG5 277
#define SPR_SPRG6 278
#define SPR_SPRG7 279
+#define SPR_EAR 282 /* MPC603e core */
#define SPR_TBL 284
#define SPR_TBU 285
#define SPR_PVR 287
#define SPR_SRR3 991
#define SPR_DBSR 1008
#define SPR_DBCR0 1010
+#define SPR_IABR 1010 /* MPC603e core */
#define SPR_IAC1 1012
#define SPR_IAC2 1013
#define SPR_DAC1 1014
#define SET_SPRG6(val) SET_REGISTER( "mtspr 278,%0", val )
#define GET_SPRG7() GET_REGISTER( "mfspr %0,279" )
#define SET_SPRG7(val) SET_REGISTER( "mtspr 279,%0", val )
+#define GET_EAR() GET_REGISTER( "mfspr %0,282" )
+#define SET_EAR(val) SET_REGISTER( "mtspr 282,%0", val )
#define GET_TBL() GET_REGISTER( "mfspr %0,284" )
#define SET_TBL(val) SET_REGISTER( "mtspr 284,%0", val )
#define GET_TBU() GET_REGISTER( "mfspr %0,285" )
#define SET_DBSR(val) SET_REGISTER( "mtspr 1008,%0", val )
#define GET_DBCR0() GET_REGISTER( "mfspr %0,1010" )
#define SET_DBCR0(val) SET_REGISTER( "mtspr 1010,%0", val )
+#define GET_IABR() GET_REGISTER( "mfspr %0,1010" )
+#define SET_IABR(val) SET_REGISTER( "mtspr 1010,%0", val )
#define GET_IAC1() GET_REGISTER( "mfspr %0,1012" )
#define SET_IAC1(val) SET_REGISTER( "mtspr 1012,%0", val )
#define GET_IAC2() GET_REGISTER( "mfspr %0,1013" )
{ SPR_SPRG5, "SPRG5" },
{ SPR_SPRG6, "SPRG6" },
{ SPR_SPRG7, "SPRG7" },
+ { SPR_EAR, "EAR" },
{ SPR_TBL, "TBL" },
{ SPR_TBU, "TBU" },
{ SPR_IC_CST, "IC_CST" },
#define CMD_TBL_CONTINUE MK_CMD_TBL_ENTRY( \
"continue", 4, 1, 0, do_bedbug_continue, \
- "break - continue from a breakpoint\n", \
+ "continue- continue from a breakpoint\n", \
" - continue from a breakpoint.\n" \
),
"puma - access PUMA FPGA\n", \
"status - print PUMA status\n" \
"puma load addr len - load PUMA configuration data\n" \
-), MK_CMD_TBL_ENTRY( \
- "spi", 3, 4, 1, do_spi, \
- "spi - read and write SPI devices\n", \
- NULL \
),
void do_puma (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
-void do_spi (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
#endif /* CONFIG_PCU_E */
/* ----------------------------------------------------------------------------*/
#undef CONFIG_8xx_CONS_SMC1
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 115200
+#define CONFIG_BAUDRATE 19200
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~( \
+ CFG_CMD_CONSOLE | \
+ CFG_CMD_BDI | \
+ CFG_CMD_LOADS | \
+ CFG_CMD_LOADB | \
+ CFG_CMD_CACHE ) )
+
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_IDE | \
- CFG_CMD_DHCP | \
CFG_CMD_DATE )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#define CONFIG_BAUDRATE 19200
+#define CONFIG_BAUDRATE 9600
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
#define CONFIG_SPI /* enable SPI driver */
+#define CONFIG_SPI_X /* 16 bit EEPROM addressing */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE | CFG_CMD_BSP)
+/* ----------------------------------------------------------------
+ * Offset to initial SPI buffers in DPRAM (used if the environment
+ * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
+ * use at an early stage. It is used between the two initialization
+ * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it
+ * far enough from the start of the data area (as well as from the
+ * stack pointer).
+ * ---------------------------------------------------------------- */
+#define CFG_SPI_INIT_OFFSET 0xB00
+
+#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32-byte page size */
+
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_DATE | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_BSP )
#define CONFIG_BOOTP_MASK \
((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-#if 1
+#if 0
/* Start port with environment in flash; switch to SPI EEPROM later */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */
* Memory controller will be used in 2 modes:
*
* - "read" mode:
- * BR4: 0x10100801 OR4: 0xffff8520
+ * BR4: 0x10100801 OR4: 0xffff8530
* - "load" mode (chip select on UPM B):
- * BR4: 0x101008c1 OR4: 0xffff8600
+ * BR4: 0x101008c1 OR4: 0xffff8630
*
* Default initialization is in "read" mode
*/
#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */
#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */
-#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2)
-#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_2_CLK)
+#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_3_CLK)
+#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_3_CLK)
#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \
BR_PS_16 | BR_MS_UPMB | BR_V)
/*
* BR5/OR5: PUMA: SMA Bus 8 Bit
- * BR5: 0x10200401 OR5: 0xffe00182
+ * BR5: 0x10200401 OR5: 0xffe0010a
*/
#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */
#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */
-#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_8_CLK | OR_EHTR)
+#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
#if PCU_E_WITH_SWAPPED_CS /* XXX */
#define CFG_BR2_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CFG_OR2_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING)
+#define CFG_OR2_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
#else /* XXX */
#define CFG_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-#define CFG_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING)
+#define CFG_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
#endif /* XXX */
/*
* BR6/OR6: PUMA: SMA Bus 16 Bit
- * BR6: 0x10600801 OR6: 0xffe00182
+ * BR6: 0x10600801 OR6: 0xffe0010a
*/
#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */
#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */
-#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_8_CLK | OR_EHTR)
+#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
#if PCU_E_WITH_SWAPPED_CS /* XXX */
#define CFG_BR1_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CFG_OR1_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING)
+#define CFG_OR1_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
#else /* XXX */
#define CFG_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CFG_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING)
+#define CFG_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
#endif /* XXX */
/*
* BR7/OR7: PUMA: external Flash
- * BR7: 0x10a00801 OR7: 0xfe000182
+ * BR7: 0x10a00801 OR7: 0xfe00010a
*/
#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */
#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */
-#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_8_CLK | OR_EHTR)
+#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
#define CFG_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define CFG_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING)
+#define CFG_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
/*
* Memory Periodic Timer Prescaler
#define CFG_PROMPT "=> "
/* What ppcboot subsytems do you want enabled? */
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))
+#define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | CFG_CMD_BEDBUG)
/* Where do the internal registers live? */
#define CFG_IMMR 0xf0000000
defined(CONFIG_WALNUT405) || \
defined(CONFIG_CPCIISER4) || \
defined(CONFIG_LWMON) || \
- defined(CONFIG_TQM8260)
+ defined(CONFIG_TQM8260) || \
+ defined(CONFIG_PCU_E)
/* $(BOARD)/eeprom.c */
void eeprom_init (void);
void eeprom_read (unsigned offset, uchar *buffer, unsigned cnt);
#endif
#if defined(CONFIG_PCU_E) && (CONFIG_COMMANDS & CFG_CMD_BSP)
-extern void spi_init (void);
-extern ssize_t spi_read (char *, size_t);
-extern ssize_t spi_write (const char *, size_t);
+extern void spi_init_f (void);
+extern void spi_init_r (void);
+extern ssize_t spi_read (uchar *, int, uchar *, int);
+extern ssize_t spi_write (uchar *, int, uchar *, int);
#endif
#ifdef CONFIG_MBX
#ifndef __VERSION_H__
#define __VERSION_H__
-#define PPCBOOT_VERSION "PPCBoot 1.0.0"
+#define PPCBOOT_VERSION "PPCBoot 1.0.1"
#endif /* __VERSION_H__ */
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# The files in this directory are free software; you can redistribute
+# them and/or modify them under the terms of the GNU General Public
+# License as published by the Free Software Foundation; either
+# version 2 of the License, or (at your option) any later version.
+#
+# These files are distributed in the hope that they will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+This directory contains scripts that help to perform certain actions
+that need to be done frequently when working with PPCBoot.
+
+They are meant as EXAMPLE code, so it is very likely that you will
+have to modify them before use.
+
+
+
+Short description:
+==================
+
+dot.kermrc:
+
+ Example for "~/.kermrc" Kermit init file for use with PPCBoot
+
+ by Wolfgang Denk, 24 Jun 2001
+
+flash_param:
+
+ "kermit" script to automatically initialize the environment
+ variables on your target. This is most useful during
+ development when your environment variables are stored in an
+ embedded flash sector which is erased whenever you install a
+ new PPCBoot image.
+
+ by Swen Anderson, 10 May 2001
+
+send_cmd:
+
+ send_cmd PPCBOOT_COMMAND
+
+ "kermit" script to send a PPCBoot command and print the
+ results. When used from a shell with history (like the bash)
+ this indirectly adds kind of history to PPCBoot ;-)
+
+ by Swen Anderson, 10 May 2001
+
+send_image:
+
+ send_image FILE_NAME OFFSET
+
+ "kermit" script to automatically download a file to the
+ target using the "loadb" command (kermit binary protocol)
+
+ by Swen Anderson, 10 May 2001
--- /dev/null
+set line /dev/ttyS0
+set speed 115200
+set carrier-watch off
+set handshake none
+set flow-control none
+robust
+set file type bin
+set file name lit
+set rec pack 1000
+set send pack 1000
+set window 5
+set prompt Kermit>
+define sz !sz \%1 \%2 \%3 \%4 \%5 \%6 \%7 \%8 \%9 < \v(line) > \v(line)
+define rz !rz \%1 \%2 \%3 \%4 \%5 \%6 \%7 \%8 \%9 < \v(line) > \v(line)
+define sx !sx \%1 \%2 \%3 \%4 \%5 \%6 \%7 \%8 \%9 < \v(line) > \v(line)
+define rx !rx \%1 \%2 \%3 \%4 \%5 \%6 \%7 \%8 \%9 < \v(line) > \v(line)
--- /dev/null
+#!/usr/bin/kermit +
+# usage: ./flash_param parameters
+# Parameters: IP Address ETH Address ERIC Number
+# Format: xxx.xxx.xxx.xxx xx:xx:xx:xx:xx:xx xxxx
+
+set line /dev/ttyS0
+set speed 115200
+set serial 8N1
+set carrier-watch off
+set handshake none
+#set flow-control none
+set flow-control xon/xoff
+#robust
+set file type bin
+set file name lit
+set rec pack 1000
+set send pack 1000
+set window 5
+set prompt Kermit>
+#robust
+# Milliseconds to pause between each OUTPUT character
+set output pacing 1
+
+out \13
+in 10 =>
+#first erase the environment memory within NVRAM
+out mw f0000000 0 200\13
+in 10 =>
+out reset\13
+in 5 autoboot
+out \13\13
+in 10 =>
+#set additional env parameter
+out setenv ethaddr \%2\13
+in 10 =>
+out setenv serial# ERIC 1.0 \%3\13
+in 10 =>
+out setenv eric_id \%3\13
+in 10 =>
+#out setenv prec_videocard_bus unknown\13
+#in 10 =>
+#out setenv prec_bios_type unknown\13
+#in 10 =>
+out setenv eric_passwd .eRIC.\13
+in 10 =>
+#out setenv bootargs root=/dev/ram ramdisk_size=8192 init=/sbin/init ip=\%1:192.168.1.100:192.168.1.254:255.255.255.0\13
+#out setenv bootargs root=/dev/ram ramdisk_size=8192 init=/sbin/init ip=\%1:192.168.0.1\13
+#out setenv bootargs root=/dev/ram ramdisk_size=8192 init=/sbin/init ip=\%1\13
+out setenv bootargs console=/dev/ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.26:/eric_root_devel ip=\%1:192.168.1.26\13
+in 10 =>
+out setenv bootcmd bootm FFC00000\13
+in 10 =>
+out saveenv\13
+in 10 =>
+out reset\13
+in 5 autoboot
+out \13\13
+in 10 =>
+quit
+exit 0
--- /dev/null
+#!/usr/bin/kermit +
+set line /dev/ttyS0
+set speed 115200
+set serial 8N1
+set carrier-watch off
+set handshake none
+set flow-control none
+robust
+set file type bin
+set file name lit
+set rec pack 1000
+set send pack 1000
+set window 5
+set prompt Kermit>
+
+#out \13
+#in 10 =>
+out \%1 \%2 \%3 \%4 \%5 \%6 \%7\13
+in 10 =>
+quit
+exit 0
+
--- /dev/null
+#!/usr/bin/kermit +
+# usage: send_image FILE_NAME OFFSET
+# e.g. send_image output.bin 1F00000
+set line /dev/ttyS0
+set speed 115200
+set serial 8N1
+set carrier-watch off
+set handshake none
+set flow-control none
+robust
+set file type bin
+set file name lit
+set rec pack 1000
+set send pack 1000
+set window 5
+set prompt Kermit>
+
+out \13
+in 10 =>
+out loadb \%2 \13
+in 10 download ...
+send \%1
+out \13
+in 10 ## Start Addr
+quit
+exit 0
projects / users / rw / ppcboot.git / commitdiff