fsl,pins = <
                        /* PD | FSEL_2 | DSE X4 */
                        MX93_PAD_ENET1_MDC__ENET_QOS_MDC                        0x51e
-                       /* SION | HYS | FSEL_2 | DSE X4 */
-                       MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO                      0x4000111e
+                       /* SION | HYS | ODE | FSEL_2 | DSE X4 */
+                       MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO                      0x4000191e
                        /* HYS | FSEL_0 | DSE no drive */
                        MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0                  0x1000
                        MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1                  0x1000
                fsl,pins = <
                        /* PD | FSEL_2 | DSE X4 */
                        MX93_PAD_ENET2_MDC__ENET1_MDC                   0x51e
-                       /* SION | HYS | FSEL_2 | DSE X4 */
-                       MX93_PAD_ENET2_MDIO__ENET1_MDIO                 0x4000111e
+                       /* SION | HYS | ODE | FSEL_2 | DSE X4 */
+                       MX93_PAD_ENET2_MDIO__ENET1_MDIO                 0x4000191e
                        /* HYS | FSEL_0 | DSE no drive */
                        MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0             0x1000
                        MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1             0x1000