ata: ahci_imx: AHB clock rate setting is not required on i.MX8QM AHCI SATA

i.MX8QM AHCI SATA doesn't need set AHB clock rate to config the vendor
specified TIMER1MS register.

Set AHB clock rate only for i.MX53 and i.MX6Q.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/1723428055-27021-4-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Niklas Cassel <cassel@kernel.org>

diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c
index 75258ed42d2ee4c82d32d3d752370fd9e2719965..4dd98368f85627343a2ceb5881d560df170b777c 100644 (file)
--- a/drivers/ata/ahci_imx.c
+++ b/drivers/ata/ahci_imx.c
@@ -872,12 +872,6 @@ static int imx_ahci_probe(struct platform_device *pdev)
                return PTR_ERR(imxpriv->sata_ref_clk);
        }
 
-       imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
-       if (IS_ERR(imxpriv->ahb_clk)) {
-               dev_err(dev, "can't get ahb clock.\n");
-               return PTR_ERR(imxpriv->ahb_clk);
-       }
-
        if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
                u32 reg_value;
 
@@ -937,11 +931,8 @@ static int imx_ahci_probe(struct platform_device *pdev)
                goto disable_clk;
 
        /*
-        * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
-        * and IP vendor specific register IMX_TIMER1MS.
-        * Configure CAP_SSS (support stagered spin up).
-        * Implement the port0.
-        * Get the ahb clock rate, and configure the TIMER1MS register.
+        * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL.
+        * Set CAP_SSS (support stagered spin up) and Implement the port0.
         */
        reg_val = readl(hpriv->mmio + HOST_CAP);
        if (!(reg_val & HOST_CAP_SSS)) {
@@ -954,8 +945,19 @@ static int imx_ahci_probe(struct platform_device *pdev)
                writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
        }
 
-       reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
-       writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
+       if (imxpriv->type != AHCI_IMX8QM) {
+               /*
+                * Get AHB clock rate and configure the vendor specified
+                * TIMER1MS register on i.MX53, i.MX6Q and i.MX6QP only.
+                */
+               imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
+               if (IS_ERR(imxpriv->ahb_clk)) {
+                       dev_err(dev, "Failed to get ahb clock\n");
+                       goto disable_sata;
+               }
+               reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
+               writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
+       }
 
        ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info,
                                      &ahci_platform_sht);