arm64: Handle mismatched cache type

Track mismatches in the cache type register (CTR_EL0), other
than the D/I min line sizes and trap user accesses if there are any.

Fixes: be68a8aaf925 ("arm64: cpufeature: Fix CTR_EL0 field definitions")
Cc: <stable@vger.kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index 8a699c708fc94b427c24135cb4d3e31d15dd00ea..be3bf3d08916ca811b9294c890adbae1f91b9783 100644 (file)
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -49,7 +49,8 @@
 #define ARM64_HAS_CACHE_DIC                    28
 #define ARM64_HW_DBM                           29
 #define ARM64_SSBD                             30
+#define ARM64_MISMATCHED_CACHE_TYPE            31
 
-#define ARM64_NCAPS                            31
+#define ARM64_NCAPS                            32
 
 #endif /* __ASM_CPUCAPS_H */

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 5d1fa928ea4b60aa89d85b9804b550ff0b57c910..5d59ff9a8da995f897a0ff6aa64610d53b0ba081 100644 (file)
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -65,11 +65,15 @@ is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
 }
 
 static bool
-has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry,
-                               int scope)
+has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
+                         int scope)
 {
        u64 mask = CTR_CACHE_MINLINE_MASK;
 
+       /* Skip matching the min line sizes for cache type check */
+       if (entry->capability == ARM64_MISMATCHED_CACHE_TYPE)
+               mask ^= arm64_ftr_reg_ctrel0.strict_mask;
+
        WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
        return (read_cpuid_cachetype() & mask) !=
               (arm64_ftr_reg_ctrel0.sys_val & mask);
@@ -615,7 +619,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
        {
                .desc = "Mismatched cache line size",
                .capability = ARM64_MISMATCHED_CACHE_LINE_SIZE,
-               .matches = has_mismatched_cache_line_size,
+               .matches = has_mismatched_cache_type,
+               .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
+               .cpu_enable = cpu_enable_trap_ctr_access,
+       },
+       {
+               .desc = "Mismatched cache type",
+               .capability = ARM64_MISMATCHED_CACHE_TYPE,
+               .matches = has_mismatched_cache_type,
                .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
                .cpu_enable = cpu_enable_trap_ctr_access,
        },