drm/amdgpu: enable mode1 reset

For sienna cichlid, add mode1 reset path for sGPU.

v2: hiding MP0/MP1 mode1 reset under AMD_RESET_METHOD_MODE1
v3: split emergency restart logic to a new patch

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 356849136d1dff5f452fbb8cb3ab1dbe933051a8..9f1240bd03106bd6669a38186ccabbe0b6b6c8cc 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -265,17 +265,21 @@ static int nv_asic_mode1_reset(struct amdgpu_device *adev)
 
        amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 
-       dev_info(adev->dev, "GPU mode1 reset\n");
-
        /* disable BM */
        pci_clear_master(adev->pdev);
 
        pci_save_state(adev->pdev);
 
-       ret = psp_gpu_reset(adev);
+       if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
+               dev_info(adev->dev, "GPU smu mode1 reset\n");
+               ret = amdgpu_dpm_mode1_reset(adev);
+       } else {
+               dev_info(adev->dev, "GPU psp mode1 reset\n");
+               ret = psp_gpu_reset(adev);
+       }
+
        if (ret)
                dev_err(adev->dev, "GPU mode1 reset failed\n");
-
        pci_restore_state(adev->pdev);
 
        /* wait for asic to come out of reset */
@@ -307,7 +311,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
 {
        struct smu_context *smu = &adev->smu;
 
-       if (!amdgpu_sriov_vf(adev) && smu_baco_is_support(smu))
+       if (smu_baco_is_support(smu))
                return AMD_RESET_METHOD_BACO;
        else
                return AMD_RESET_METHOD_MODE1;
@@ -319,15 +323,16 @@ static int nv_asic_reset(struct amdgpu_device *adev)
        struct smu_context *smu = &adev->smu;
 
        if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
+               dev_info(adev->dev, "GPU BACO reset\n");
+
                ret = smu_baco_enter(smu);
                if (ret)
                        return ret;
                ret = smu_baco_exit(smu);
                if (ret)
                        return ret;
-       } else {
+       } else
                ret = nv_asic_mode1_reset(adev);
-       }
 
        return ret;
 }

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index d96e8334b5e2a66971f1b95a2cb1db20c98754d3..a00ec67f920340e26ae5cb108f6b8d925f158cb6 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -2057,7 +2057,7 @@ static bool navi10_is_baco_supported(struct smu_context *smu)
        struct amdgpu_device *adev = smu->adev;
        uint32_t val;
 
-       if (!smu_v11_0_baco_is_support(smu))
+       if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
                return false;
 
        val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);

diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 4545ea9828b985b0c2b666fc9d543bd07cf81c7a..35e5a4b4a5e3a5f7c41428a35ffa2c91e4953076 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -1773,7 +1773,7 @@ static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
        struct amdgpu_device *adev = smu->adev;
        uint32_t val;
 
-       if (!smu_v11_0_baco_is_support(smu))
+       if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
                return false;
 
        val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);