As pointed out by Stephen Rothwell, commit 
e52117638b79 ("ARM: dts:
omap3: Add DT entries for OMAP 3 ISP") conflicts with 
b8845074cfbb
("ARM: dts: omap3: add minimal l4 bus layout with control module support")
in non-obvious ways, causing a build failure when both patches
are present.
This merges the two branches that introduce the respective changes
into the next/late branch to resolve the way that Stephen suggested,
as confirmed by Tony.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lkml.org/lkml/2015/4/6/436
Acked-by: Tony Lindgren <tony@atomide.com>
 
                        pinctrl-single,register-width = <16>;
                        pinctrl-single,function-mask = <0xff1f>;
                };
 -                      syscon = <&omap3_scm_general 0xdc>;
+ 
+               isp: isp@480bc000 {
+                       compatible = "ti,omap3-isp";
+                       reg = <0x480bc000 0x12fc
+                              0x480bd800 0x017c>;
+                       interrupts = <24>;
+                       iommus = <&mmu_isp>;
++                      syscon = <&scm_conf 0xdc>;
+                       ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
+                       #clock-cells = <1>;
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+               };
        };
  };
  
 
                        pinctrl-single,register-width = <16>;
                        pinctrl-single,function-mask = <0xff1f>;
                };
 -                      syscon = <&omap3_scm_general 0x2f0>;
+ 
+               isp: isp@480bc000 {
+                       compatible = "ti,omap3-isp";
+                       reg = <0x480bc000 0x12fc
+                              0x480bd800 0x0600>;
+                       interrupts = <24>;
+                       iommus = <&mmu_isp>;
++                      syscon = <&scm_conf 0x2f0>;
+                       ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
+                       #clock-cells = <1>;
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+               };
        };
  };